Hitachi SH7750 Hardware Manual page 69

Table 1.2 Pin Functions (cont)
Pin
No. No. Pin Name
174 E19 D63
175 F18 VDDQ
176 F17 VSSQ
177 E17 VSSQ
178 E18 RD/WR2
179 D20 MD0/SCK
180 D19 MD1/TXD2 I/O
181 D18 MD2/RXD2 I
IRL0
182 C20
IRL1
183 C19
IRL2
184 B20
IRL3
185 C18
186 A20 NMI
187 B19 XTAL2
188 A19 EXTAL2
189 B18 VSS-RTC
190 A18 VDD-RTC
191 D17 CA
192 C17 VSS
193 B17 VDDQ
CTS2
194 C16
195 A17 TCLK
196 B16 MD8/RTS2 I/O
I/O Function
I/O Data
Power IO VDD (3.3 V)
Power IO GND (0 V)
Power IO GND (0 V)
O RD/WR
I/O Mode/SCI
clock
Mode SCIF
data output
Mode/SCIF
data input
I Interrupt 0
I Interrupt 1
I Interrupt 2
I Interrupt 3
I Nonmaskable
interrupt
O RTC crystal
resonator pin
I RTC crystal
resonator pin
Power RTC GND
(0 V)
Power RTC VDD
(3.3 V)
2
*
I
Power Internal GND
(0 V)
Power IO VDD (3.3 V)
I/O SCIF data
control (CTS)
I/O RTC/TMU
clock
Mode/SCIF
data control
(RTS)
Reset SRAM DRAM
RD/WR RD/WR RD/WR
MD0 SCK SCK
MD1 TXD2 TXD2
MD2 RXD2 RXD2
RTS2 RTS2
MD8
Memory Interface
SDRAM PCMCIA MPX
SCK SCK
TXD2 TXD2
RXD2 RXD2
RTS2 RTS2
Rev. 6.0, 07/02, page 19 of 986
ACCSIZE2
RD/WR
SCK
TXD2
RXD2
RTS2