Figure 22.51 Dram Bus Cycle: Dram Self-Refresh (Trc[2:0] = 001) - Hitachi SH7750 Hardware Manual

TRr1
CKIO
t
AD
A25–A0
t
CSD
t
RWD
RD/
t
RASD
t
CASD1
t
WDD
D63–D0
(write)
t
DACD
DACKn
(SA: IO ← memory)
t
DACD
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high

Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)

Rev. 6.0, 07/02, page 914 of 986
TRr2 TRr3 TRr4
t
RASD
t
CASD1
TRr5 Trc Trc
t
RASD
t
CASD1
Trc