Hitachi SH7750 Hardware Manual page 745

In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR2 in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
the first is checked.
b. The SCIF checks whether receive data can be transferred from the receive shift register
(SCRSR2) to SCFRDR2.
c. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun
error has occurred.
d. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
set.
If b, c, and d checks are passed, the receive data is stored in SCFRDR2.
Note: Reception continues when parity error, framing error occurs.
4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR2 is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Figure 16.11 shows an example of the operation for reception in asynchronous mode.
Rev. 6.0, 07/02, page 695 of 986