Figure 13.13 Sram Interface Read-Strobe Negate Timing (Ans = 1, Anw = 4, Anh = 2) 395 Figure 13.14 Example Of Dram Connection (64-Bit Data Width, Area 3) - Hitachi SH7750 Hardware Manual

Signals used for connection when DRAM is connected to area 3 are RAS, CAS0 to CAS7, and
RD/WR. CAS2 to CAS7 are not used when the data width is 16 bits. When DRAM is connected
to areas 2 and 3, the signals for area 2 DRAM connection are RAS2, CAS4 to CAS7, and RD/WR,
and those for area 3 DRAM connection are RAS, CAS0 to CAS3, and RD/WR.
In addition to normal read and write access modes, fast page mode is supported for burst access.
For DRAM connected to areas 2 and 3, EDO mode, which enables the DRAM access time to be
increased, is supported.
SH7750 Series
A12–A3
RD/
D63–D48
D47–D32
D31–D16
D15–D0
Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3)
Rev. 6.0, 07/02, page 396 of 986
1M × 16-bit
DRAM
A9–A0
I/O15–I/O0
A9–A0
I/O15–I/O0
A9–A0
I/O15–I/O0
A9–A0
I/O15–I/O0