Hitachi SH7750 Hardware Manual page 515

Tm1 Tmd1w Tmd1 Tmd2
CKIO
/
D31–D0
A D0 D1
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.65 MPX Interface Timing 1
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bytes)
Rev. 6.0, 07/02, page 465 of 986