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10.3
Clock Operating Modes
Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various
combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency
division ratio).
Table 10.4 shows FRQCR settings and internal clock frequencies.
Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)
External
Pin Combination
Clock
Operating
Mode
MD2
MD1
0
0
0
1
2
1
3
4
1
0
5
Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating
mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f
Timing.
Table 10.3 (2) Clock Operating Modes (SH7750R)
External
Pin Combination
Clock
Operating
Mode
MD2
MD1
0
0
0
1
2
1
3
4
1
0
5
6
1
Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f
Timing.
1/2
Frequency
MD0
Divider
PLL1 PLL2
0
Off
On
1
Off
On
0
On
On
1
Off
On
0
On
On
1
Off
On
) and CKIO clock output (f
EX
MD0
PLL1
0
On (×12) On
1
On (×12) On
0
On (×6)
1
On (×12) On
0
On (×6)
1
On (×12) On
0
Off (×6)
) and CKIO clock output (f
EX
(vs. Input Clock)
CPU
Clock
On
6
On
6
On
3
On
6
On
3
On
6
) in section 22.3.1, Clock and Control Signal
OP
Frequency
(vs. Input Clock)
CPU
Bus
Clock
Clock
PLL2
12
3
12
3/2
On
6
2
12
4
On
6
3
12
6
Off
1
1/2
) in section 22.3.1, Clock and Control Signal
OP
Frequency
Peripheral
Bus
Module
FRQCR
Clock
Clock
Initial Value
3/2
3/2
H'0E1A
1
1
H'0E23
1
1/2
H'0E13
2
1
H'0E13
3/2
3/4
H'0E0A
3
3/2
H'0E0A
Peripheral
FRQCR
Module Clock
Initial Value
3
H'0E1A
3/2
H'0E2C
1
H'0E13
2
H'0E13
3/2
H'0E0A
3
H'0E0A
1/2
H'0808
Rev. 6.0, 07/02, page 253 of 986
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