Hitachi SH7750 Hardware Manual page 378

Bit 26—Data pin Pullup Resistor Control (DPUP) (SH7750R only): Controls the pullup
resistance of the data pins (D63 to D0). It is initialized at a power-on reset. The pins are not pulled
up when access is performed or when the bus is released, even if the ON setting is selected.
Bit 26: DPUP
0
1
Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor
status for control input pins (NMI, IRL0–IRL3, BREQ, MD6/IOIS16, RDY). IPUP is initialized
by a power-on reset.
Bit 25: IPUP
0
1
Bit 24—Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor
status for control output pins (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, RAS2, CE2A, CE2B,
RD2, RD/WR2) when high-impedance. OPUP is initialized by a power-on reset.
Bit 24: OPUP
0
1
Bit 21—Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 21: A1MBC
0
1
Rev. 6.0, 07/02, page 328 of 986
Description
Sets pullup resistance of data pins (D63 to D0) ON
Sets pullup resistance of data pins (D63 to D0) OFF
Description
Pull-up resistor is on for control input pins (NMI, IRL0–IRL3, BREQ,
MD6/IOIS16, RDY)
Pull-up resistor is off for control input pins (NMI, IRL0–IRL3, BREQ,
MD6/IOIS16, RDY)
Description
Pull-up resistor is on for control output pins (A[25:0], BS, CSn, RD, WEn,
RD/WR, RAS, RAS2, CE2A, CE2B, RD2, RD/WR2)
Pull-up resistor is off for control output pins (A[25:0], BS, CSn, RD, WEn,
RD/WR, RAS, RAS2, CE2A, CE2B, RD2, RD/WR2)
Description
Area 1 SRAM is set to normal mode
Area 1 SRAM is set to byte control mode
(Initial value)
(Initial value)
(Initial value)
(Initial value)