Figure 4.3 Configuration Of Operand Cache (Sh7750R) - Hitachi SH7750 Hardware Manual

Effective address
31 26 25
OIX
ORA
Entry
selection
22
9
0
MMU
19
511
Compare
way 0

Figure 4.3 Configuration of Operand Cache (SH7750R)

RAM area
judgment
[13]
Address array
(way 0, way 1)
Tag address U V
19 bits 1 bit 1 bit
Compare
way 1
Hit signal
13 12 10
[12:5]
Data array (way 0, way 1)
3
LW0 LW1 LW2 LW3
32 bits 32 bits 32 bits 32 bits
Read data
Rev. 6.0, 07/02, page 101 of 986
5 4 2 0
Longword (LW)
selection
LW4 LW5 LW6 LW7
32 bits 32 bits 32 bits 32 bits
Write data
LRU
1 bit