Hitachi SH7750 Hardware Manual page 258

(e) Flow dependency
MOV R0,R1
ADD R2,R1
ADD R2,R1
MOV.L @R1,R1
next
MOV.L @R1,R1
ADD R0,R1
next
MOV.L @R1,R1
SHAD R1,R2
next
FADD FR1,FR2
STS FPUL,R1
STS FPSCR,R2
FADD DR0,DR2
FMOV FR3,FR5
FMOV FR2,FR4
FLOAT FPUL,DR0
FMOV.S FR0,@-R15
FLDI1 FR3
FIPR FV0,FV4
FMOV @R1,XD14
FTRV XMTRX,FV0
Rev. 6.0, 07/02, page 208 of 986
Zero-cycle latency
EX
I D NA
EX
I D NA
1-cycle latency
EX
I D NA
i EX
I D
I
...
1 stall cycle
EX
I D MA
I
D
I
... 1 stall cycle
EX
I D MA
I
D
I
...
2 stall cycles
F1
I D F2
EX
I D
I
2 stall cycles
I F1 F2
D
F1
d
d
I
I
F1
I D F2
F1
d
D
I
Zero-cycle latency
EX
I D NA
D
I
EX
I D MA
D
I
3 stall cycles
Figure 8.3 Examples of Pipelined Execution (cont)
S
S
S
MA S
2-cycle latency
S
EX
NA S
2-cycle latency
1-cycle increase
S
EX
d NA S
4-cycle latency for FPSCR
FS
NA S
D EX
NA
FS
F2
FS
F1
F2
FS
F1
d F2 FS
F1
d F2
F1
3-cycle latency for upper/lower FR
FR1 write
FS
FR0 write
F2 FS
EX
MA S
3-cycle increase
S
F0
d F1 F2
3 stall cycles
2-cycle latency
1-cycle increase
S
F0
d F1
F2
F0
d F1
F0
d
d
The following instruction, ADD, is not
stalled when executed after an instruction
with zero-cycle latency, even if there is
dependency.
ADD and MOV.L are not executed in
parallel, since MOV.L references the result
of ADD as its destination address.
Because MOV.L and ADD are not fetched
simultaneously in this example, ADD is
stalled for only 1 cycle even though the
latency of MOV.L is 2 cycles.
Due to the flow dependency between the
load and the SHAD/SHLD shift amount,
the latency of the load is increased to 3
cycles.
S
7-cycle latency for lower FR
8-cycle latency for upper FR
FR3 write
FS
FR2 write
F2
FS
D EX
NA S
D EX
NA
FS
FS
F2 FS
F1 F2 FS
F0 F1
F2
FS
S