Hitachi SH7750 Hardware Manual page 566

Sh7750 series superh risc engine
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Transfer on channel 0
Initial priority order
Priority order after transfer
Transfer on channel 1
Initial priority order
Priority order after transfer
Transfer on channel 2
Initial priority order
Priority order after transfer
Priority after transfer due to
issuance of a transfer request
for channel 1 only.
Transfer on channel 3
Initial priority order
Priority order after transfer
Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously
for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The
operation of the DMAC in this case is as follows.
Rev. 6.0, 07/02, page 516 of 986
CH0 > CH1 > CH2 > CH3
CH1 > CH2 > CH3 > CH0
CH0 > CH1 > CH2 > CH3
CH2 > CH3 > CH0 > CH1
CH0 > CH1 > CH2 > CH3
CH3 > CH0 > CH1 > CH2
CH2 > CH3 > CH0 > CH1
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
Figure 14.3 Round Robin Mode
Channel 0 is given the lowest
priority.
When channel 1 is given the
lowest priority, the priority of
channel 0, which was higher
than channel 1, is also
shifted simultaneously.
When channel 2 is given the
lowest priority, the priorities of
channels 0 and 1, which were
higher than channel 2, are
also shifted simultaneously. If
there is a transfer request for
channel 1 only immediately
afterward, channel 1 is given
the lowest priority and the
priorities of channels 3 and 0
are simultaneously shifted
down.
No change in priority order

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