Table 21.3 Configuration Of The Boundary Scan Register (1) - Hitachi SH7750 Hardware Manual

Table 21.3 Configuration of the Boundary Scan Register (1)

No. Pin Name
from TDI
CKIO2ENB
345
344 MD6/IOIS16
343 STATUS1
342 STATUS1
341 STATUS0
340 STATUS0
339 A1
338 A1
337 A0
336 A0
335 DACK1
334 DACK1
333 DACK0
332 DACK0
331 MD5/RAS2
330 MD5/RAS2
329 MD5/RAS2
328 MD4/CE2B
327 MD4/CE2B
326 MD4/CE2B
325 MD3/CE2A
324 MD3/CE2A
323 MD3/CE2A
322 A25
321 A25
320 A24
319 A24
318 A23
317 A23
316 A22
315 A22
314 A21
313 A21
312 A20
311 A20
310 A19
Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW.
Type No. Pin Name
309 A19
IN 308 A18
IN 307 A18
CTL 306 SCK2/MRESET
OUT 305 SCK2/MRESET
CTL 304 SCK2/MRESET
OUT 303 MD7/TXD
CTL 302 MD7/TXD
OUT 301 MD7/TXD
CTL 300 MD8/RTS2
OUT 299 MD8/RTS2
CTL 298 MD8/RTS2
OUT 297 TCLK
CTL 296 TCLK
OUT 295 TCLK
IN 294 CTS2
CTL 293 CTS2
OUT 292 CTS2
IN 291 NMI
IRL3
CTL 290
IRL2
OUT 289
IRL1
IN 288
IRL0
CTL 287
OUT 286 MD2/RXD2
CTL 285 MD1/TXD2
OUT 284 MD1/TXD2
CTL 283 MD1/TXD2
OUT 282 MD0/SCK
CTL 281 MD0/SCK
OUT 280 MD0/SCK
CTL 279 RD/WR2
OUT 278 RD/WR2
CTL 277 D63
OUT 276 D63
CTL 275 D63
OUT 274 D48
CTL 273 D48
Type No. Pin Name
OUT 272 D48
CTL 271 D62
OUT 270 D62
IN 269 D62
CTL 268 D49
OUT 267 D49
IN 266 D49
CTL 265 D61
OUT 264 D61
IN 263 D61
CTL 262 D50
OUT 261 D50
IN 260 D50
CTL 259 D60
OUT 258 D60
IN 257 D60
CTL 256 D51
OUT 255 D51
IN 254 D51
IN 253 D59
IN 252 D59
IN 251 D59
IN 250 D52
IN 249 D52
IN 248 D52
CTL 247 D58
OUT 246 D58
IN 245 D58
CTL 244 D53
OUT 243 D53
CTL 242 D53
OUT 241 D57
IN 240 D57
CTL 239 D57
OUT 238 D54
IN 237 D54
CTL 236 D54
Rev. 6.0, 07/02, page 807 of 986
Type
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT