Instruction Set; Table 7.2 Notation Used In Instruction List - Hitachi SH7750 Hardware Manual

7.3

Instruction Set

Table 7.2 shows the notation used in the following SH instruction list.
Table 7.2 Notation Used in Instruction List
Item Format
Instruction OP.Sz SRC, DEST
mnemonic
Summary of
operation
MSB ↔ LSB
Instruction code
Privileged mode
T bit Value of T bit after
instruction execution
Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand(s).
Description
OP: Operation code
Sz: Size
SRC: Source
DEST: Source and/or destination operand
→, ←:
Transfer direction
(xx): Memory operand
M/Q/T: SR flag bits
&: Logical AND of individual bits
|: Logical OR of individual bits
∧
: Logical exclusive-OR of individual bits
~: Logical NOT of individual bits
<<n, >>n: n-bit shift
mmmm: Register number (Rm, FRm)
nnnn: Register number (Rn, FRn)
0000: R0, FR0
0001: R1, FR1
:
1111: R15, FR15
mmm: Register number (DRm, XDm, Rm_BANK)
nnn: Register number (DRm, XDm, Rn_BANK)
000: DR0, XD0, R0_BANK
001: DR2, XD2, R1_BANK
:
111: DR14, XD14, R7_BANK
mm: Register number (FVm)
nn: Register number (FVn)
00: FV0
01: FV4
10: FV8
11: FV12
iiii: Immediate data
dddd: Displacement
"Privileged" means the instruction can only be executed
in privileged mode.
—: No change
Rev. 6.0, 07/02, page 179 of 986