Hitachi SH7750 Hardware Manual page 512

Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4
CKIO
/
D63–D0
A D0 D1 D2 D3
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.62 MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits,
Transfer Data Size: 32 Bytes)
Rev. 6.0, 07/02, page 462 of 986