Hitachi SH7750 Hardware Manual page 635

DMAOR DMAOR
Bit 9 Bit 8
PR1 PR0
0 0
0 1
1 0
1 1
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be
cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in
section 14.2.5, DMA Operation Register (DMAOR)
Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of
whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all
channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing
0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5,
DMA Operation Register (DMAOR)
Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME
bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is
enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are
suspended.
Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or
when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the
DME bit in section 14.2.5, DMA Operation Register (DMAOR)
Description
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1
CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7
Round robin mode
(Initial value)
Rev. 6.0, 07/02, page 585 of 986