Break Bus Cycle Register B (Bbrb); Break Control Register (Brcr) - Hitachi SH7750 Hardware Manual

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Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the

corresponding bit of the channel B break data B31 to B0 (BDB31–BDB0) set in BDRB is to be

Bit 31–0: BDMBn

Note: When the data bus value is included in the break conditions, the operand size should be

specified. When byte size is specified, set the same data in bits 15–8 and 7–0 of BDRB and

20.2.11 Break Bus Cycle Register B (BBRB)

BBRB is the channel B bus break register. The bit configuration is the same as for BBRA.

Initial value:

Initial value:

Note: *: Undefined

The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether

channels A and B are to be used as two independent channels or in a sequential condition, (2)

whether the break is to be effected before or after instruction execution, (3) whether the BDRB

function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE

bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The

value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual

reset, so these bits should be initialized by software as necessary.

Channel B break data bit BDBn is included in break conditions

Channel B break data bit BDBn is masked, and not included in break

Rev. 6.0, 07/02, page 783 of 986

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