Hitachi SH7750 Hardware Manual page 42

Figure 16.4 MD1/TxD2 Pin ................................................................................................ 683
Figure 16.5 MD2/RxD2 Pin ................................................................................................ 683
Figure 16.6 Sample SCIF Initialization Flowchart.............................................................. 689
Figure 16.7 Sample Serial Transmission Flowchart............................................................ 690
Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity,
One Stop Bit) ................................................................................................... 692
Figure 16.9 Example of Operation Using Modem Control (CTS2) .................................... 692
Figure 16.10 Sample Serial Reception Flowchart (1) ........................................................... 693
Figure 16.10 Sample Serial Reception Flowchart (2) ........................................................... 694
Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity,
One Stop Bit) ................................................................................................... 696
Figure 16.12 Example of Operation Using Modem Control (RTS2) .................................... 696
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode................................. 699
Figure 16.14 Overrun Error Flag........................................................................................... 701
Figure 17.1 Block Diagram of Smart Card Interface .......................................................... 704
Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections ........................ 711
Figure 17.3 Smart Card Interface Data Format ................................................................... 712
Figure 17.4 TEND Generation Timing ............................................................................... 714
Figure 17.5 Sample Start Character Waveforms ................................................................. 715
Figure 17.6 Difference in Clock Output According to GM Bit Setting .............................. 717
Figure 17.7 Sample Initialization Flowchart ....................................................................... 719
Figure 17.8 Sample Transmission Processing Flowchart.................................................... 721
Figure 17.9 Sample Reception Processing Flowchart ......................................................... 723
Figure 17.10 Receive Data Sampling Timing in Smart Card Mode...................................... 725
Figure 17.11 Retransfer Operation in SCI Receive Mode..................................................... 726
Figure 17.12 Retransfer Operation in SCI Transmit Mode ................................................... 727
Figure 17.13 Procedure for Stopping and Restarting the Clock............................................ 728
Figure 18.1 16-Bit Port........................................................................................................ 732
Figure 18.2 4-Bit Port.......................................................................................................... 733
Figure 18.3 MD0/SCK Pin.................................................................................................. 734
Figure 18.4 MD7/TxD Pin .................................................................................................. 735
Figure 18.5 RxD Pin............................................................................................................ 735
Figure 18.6 MD1/TxD2 Pin ................................................................................................ 736
Figure 18.7 MD2/RxD2 Pin ................................................................................................ 736
CTS2 Pin.......................................................................................................... 737
Figure 18.8
Figure 18.9 MD8/RTS2 Pin ................................................................................................ 738
Figure 19.1 Block Diagram of INTC .................................................................................. 752
Figure 19.2 Example of IRL Interrupt Connection ............................................................. 755
Figure 19.3 Interrupt Operation Flowchart ......................................................................... 769
Figure 20.1 Block Diagram of User Break Controller ........................................................ 774
Figure 20.2 User Break Debug Support Function Flowchart .............................................. 794
Figure 21.1 Block Diagram of H-UDI Circuit .................................................................... 800
Figure 21.2 TAP Control State Transition Diagram............................................................ 810
Rev. 6.0, 07/02, page xlii of I