Register Configuration; Pin Configuration; Table 9.2 Power-Down Mode Registers; Table 9.3 Power-Down Mode Pins - Hitachi SH7750 Hardware Manual

9.1.2

Register Configuration

Table 9.2 shows the registers used for power-down mode control.
Table 9.2 Power-Down Mode Registers
Name Abbreviation
Standby control STBCR
register
Standby control STBCR2
register 2
Clock stop CLKSTP00
register 00*
Clock release CLKSTPCLR00
register 00*
Note: * SH7750R only
9.1.3

Pin Configuration

Table 9.3 shows the pins used for power-down mode control.
Table 9.3 Power-Down Mode Pins
Pin Name
Processor status 1
Processor status 0
Hardware standby
request
(SH7750S and
SH7750R only)
Notes: H: High level
L: Low level
R/W
R/W
R/W
R/W
W
Abbreviation I/O
STATUS1 Output
STATUS0
CA Input
Initial Value P4 Address
H'00 H'FFC00004
H'00 H'FFC00010
H'00000000 H'FE0A0000
H'00000000 H'FE0A0008
Function
Indicate the processor's operating status.
(STATUS1, STATUS0)
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
Transits to hardware standby mode by a
low-level input to the pin.
Rev. 6.0, 07/02, page 223 of 986
Area 7 Access
Address Size
H'1FC00004 8
H'1FC00010 8
H'1E0A0000 32
H'1E0A0008 32