Table 17.8 Register Settings And Sck Pin State - Hitachi SH7750 Hardware Manual

The bit rate error is given by the following equation:
Error (%) =
Table 17.8 shows the relationship between the smart card interface transmit/receive clock register
settings and the output state.

Table 17.8 Register Settings and SCK Pin State

Register Values
Setting SMIF GM
1
1 *
1 0
1 0
2
2 *
1 1
1 1
2
3 *
1 1
1 1
Notes: *1 The SCK output state changes as soon as the CKE0 bit setting is changed.
Clear the CKE1 bit to 0.
*2 Stopping and starting the clock by changing the CKE0 bit setting does not affect the
clock duty cycle.
Width is
Port value
undefined
SCK
Specified
CKE1 value
width
SCK
Figure 17.6 Difference in Clock Output According to GM Bit Setting
P φ
1488 × 2 × B × (N + 1)
2n–1
CKE1 CKE0
0 0
0 1
0 0
0 1
1 0
1 1
(a) When GM = 0
(b) When GM = 1
× 10 – 1 × 100
6
SCK Pin
Output State
Port Determined by setting of SPB1IO
and SPB1DT bits in SCSPTR1
SCK (serial clock) output state
Low output Low-level output state
SCK (serial clock) output state
High output High-level output state
SCK (serial clock) output state
Specified
width
Rev. 6.0, 07/02, page 717 of 986
Width is
undefined
Port value
CKE1 value