Hitachi SH7750 Hardware Manual page 403

on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name: TRWL2 TRWL1 TRWL0
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit 31—RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set
BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3
are both designated as synchronous DRAM interface.
Bit 31: RASD
0
1
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
31 30
RASD MRSET TRC2
0 0
R/W R/W R/W
23 22
TCAS — TPC2
0 0
R/W R R/W
15 14
0 0
R/W R/W R/W
7 6
SZ0 AMXEXT AMX2
0 0
R/W R/W R/W
Description
Normal mode
RAS down mode
29 28 27
TRC1 TRC0
0 0 0
R/W R/W
21 20 19
TPC1 TPC0
0 0 0
R/W R/W
13 12 11
TRAS2 TRAS1
0 0 0
R/W R/W
5 4 3
AMX1 AMX0
0 0 0
R/W R/W
26 25
— —
0 0
R R
18 17
— RCD1
0 0
R R/W
10 9
TRAS0 BE
0 0
R/W R/W
2 1
RFSH RMODE
0 0
R/W R/W
(Initial value)
Rev. 6.0, 07/02, page 353 of 986
24
—
0
R
16
RCD0
0
R/W
8
SZ1
0
R/W
0
EDO
MODE
0
R/W