Hitachi SH7750 Hardware Manual page 992

Table A.1 Address List (cont)
Module Register P4 Address
H-UDI SDIR H'FFF0 0000 H'1FF0 0000 16
H-UDI SDDR H'FFF0 0008 H'1FF0 0008 32
5
SDINT *
H-UDI H'FFF0 0014 H'1FF0 0014 16
Notes: *1 With control registers, the above addresses in the physical page number field can be
accessed by means of a TLB setting. When these addresses are referenced directly
without using the TLB, operations are limited.
*2 Includes undefined bits. See the descriptions of the individual modules.
*3 Use word-size access when writing. Perform the write with the upper byte set to H'5A or
H'A5, respectively. Byte- and longword-size writes cannot be used.
Use byte-size access when reading.
*4 SH7750S, SH7750R only
*5 SH7750R only
*6 Includes power-down states
Rev. 6.0, 07/02, page 942 of 986
Area 7 Power-On
1
Address *
Reset
Size
H'FFFF *
Undefined
H'0000
Manual
Reset
Sleep Standby
2
Held Held
Held Held
Held Held
Synchro-
nization
Clock
Held Pclk
Held Pclk
Held Pclk