Hitachi SH7750 Hardware Manual page 493

T1 Tw Tw TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2
CKIO
A25–A5
A4–A0
RD/
D63–D0
(read)
DACKn
(SA: IO ← memory)
Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed.
2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.47 Burst ROM Wait Access Timing
Rev. 6.0, 07/02, page 443 of 986