Figure 13.22 (2) Dram Burst Bus Cycle, Ras Down Mode Continuation (Fast Page Mode, Rcd = 0, Anw = 0) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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End of RAS down mode

(SA: IO ← memory)

(SA: IO → memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation

(Fast Page Mode, RCD = 0, AnW = 0)

Rev. 6.0, 07/02, page 406 of 986

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