Register Settings; Table 17.3 Smart Card Interface Register Settings - Hitachi SH7750 Hardware Manual

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If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)

to request retransmission of the data. After outputting the error signal for the prescribed length

of time, the receiving station places the signal line in the high-impedance state again. The

signal line is pulled high again by a pull-up resistor.

5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data

If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data.

Register Settings

Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or

1 must be set to the value shown. The setting of other bits is described below.

Note: A dash indicates an unused bit.

Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag

setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to

select the clock output state.

The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the

inverse convention type.

Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section

17.3.5, Clock.

Rev. 6.0, 07/02, page 713 of 986

SPB1DT SPB0IO

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