Refresh Timer Control/Status Register (Rtcsr) - Hitachi SH7750 Hardware Manual

LMODE: RAS-CAS latency
BL: Burst length
WT: Wrap type (0: Sequential)
BL LMODE
000: Reserved 000: Reserved
001: Reserved 001: 1
010: 4 010: 2
011: 8 011: 3
100: Reserved 100: Reserved
101: Reserved 101: Reserved
110: Reserved 110: Reserved
111: Reserved 111: Reserved
Note: * SH7750R only.

13.2.11 Refresh Timer Control/Status Register (RTCSR)

The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
specifies the refresh cycle and whether interrupts are to be generated.
RTCSR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.15,
Notes on Accessing Refresh Control Registers.
Rev. 6.0, 07/02, page 364 of 986
15 14 13
— —
0 0
— —
7 6
CMF CMIE CKS2
0 0
R/W R/W R/W
12 11
— — —
0 0 0
— — —
5 4 3
CKS1 CKS0
0 0 0
R/W R/W
10 9
— — —
0 0
— — —
2 1
OVF OVIE LMTS
0 0
R/W R/W R/W
8
0
0
0