Hitachi SH7750 Hardware Manual page 34

Appendix H Power-On and Power-Off Procedures
Appendix I Product Code Lineup
Index
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Figures
Figure 1.1 Block Diagram of SH7750 Series Functions ...................................................
Figure 1.2 Pin Arrangement (256-Pin BGA) .................................................................... 10
Figure 1.3 Pin Arrangement (208-Pin QFP)...................................................................... 11
Figure 1.4 Pin Arrangement (264-Pin CSP)...................................................................... 12
Figure 2.1 Data Formats.................................................................................................... 41
Figure 2.2 CPU Register Configuration in Each Processor Mode .................................... 44
Figure 2.3 General Registers ............................................................................................. 46
Figure 2.4 Floating-Point Registers................................................................................... 48
Figure 2.5 Data Formats In Memory................................................................................. 53
Figure 2.6 Processor State Transitions .............................................................................. 55
Figure 3.1 Role of the MMU............................................................................................. 59
Figure 3.2 MMU-Related Registers .................................................................................. 61
Figure 3.3 Physical Address Space (MMUCR.AT = 0) .................................................... 65
Figure 3.4 P4 Area ............................................................................................................ 66
Figure 3.5 External Memory Space................................................................................... 67
Figure 3.6 Virtual Address Space (MMUCR.AT = 1) ...................................................... 68
Figure 3.7 UTLB Configuration........................................................................................ 71
Figure 3.8 Relationship between Page Size and Address Format ..................................... 72
Figure 3.9 ITLB Configuration ......................................................................................... 75
Figure 3.10 Flowchart of Memory Access Using UTLB .................................................... 76
Figure 3.11 Flowchart of Memory Access Using ITLB...................................................... 77
Figure 3.12 Operation of LDTLB Instruction ..................................................................... 79
Figure 3.13 Memory-Mapped ITLB Address Array ........................................................... 88
Figure 3.14 Memory-Mapped ITLB Data Array 1.............................................................. 89
Figure 3.15 Memory-Mapped ITLB Data Array 2.............................................................. 90
Figure 3.16 Memory-Mapped UTLB Address Array.......................................................... 91
Figure 3.17 Memory-Mapped UTLB Data Array 1 ............................................................ 92
Figure 3.18 Memory-Mapped UTLB Data Array 2 ............................................................ 93
Figure 4.1 Cache and Store Queue Control Registers ....................................................... 97
Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S) .................................... 100
Figure 4.3 Configuration of Operand Cache (SH7750R).................................................. 101
Figure 4.4 Configuration of Write-Back Buffer................................................................ 105
Figure 4.5 Configuration of Write-Through Buffer .......................................................... 105
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)................................ 109
Figure 4.7 Configuration of Instruction Cache (SH7750R) .............................................. 110
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