Control Signal Timing; Table 22.34 Control Signal Timing (1) - Hitachi SH7750 Hardware Manual

22.3.2

Control Signal Timing

Table 22.34 Control Signal Timing (1)

Item Symbol Min
BREQ setup
t
BREQS
time
BREQ hold
t
BREQH
time
BACK delay
t
BACKD
time
Bus tri-state t
BOFF1
delay time
Bus tri-state t
BOFF2
delay time
to standby
mode
Bus buffer t
BON1
on time
t
Bus buffer
BON2
on time from
standby
STATUS0/1 t
STD1
delay time
STATUS0/1 t
STD2
delay time
to standby
Note: * V = 3.0 to 3.6 V, V
DDQ
Rev. 6.0, 07/02, page 868 of 986
HD6417750 HD6417750
RBP240 RBP200
* *
Max Min Max
2 — 2.5 —
1.5 — 1.5 —
— 5.3 — 6
— 12 — 12
— 2 — 2
— 12 — 12
— 1 — 1
— 5 — 6
— 2 — 2
= typ. 1.5 V, Ta = –20 to +75°C, C
DD
HD6417750 HD6417750
RF240 RF200
* *
Min Max Min Max
3.5 — 3.5 —
1.5 — 1.5 —
— 6 — 6
— 12 — 12
— 2 — 2
— 12 — 12
— 1 — 1
— 6 — 6
— 2 — 2
= 30 pF, PLL2 on
L
Unit Figure Notes
ns 22.13
ns 22.13
ns 22.13
ns 22.13
t 22.14
cyc
ns 22.13
t 22.14
cyc
ns 22.14
t 22.14
cyc