Hitachi SH7750 Hardware Manual page 32

19.4 INTC Operation ................................................................................................................ 768
19.4.1 Interrupt Operation Sequence .............................................................................. 768
19.4.2 Multiple Interrupts ............................................................................................... 770
19.4.3 Interrupt Masking with MAI Bit.......................................................................... 770
19.5 Interrupt Response Time................................................................................................... 771
Section 20 User Break Controller (UBC)
20.1 Overview........................................................................................................................... 773
20.1.1 Features................................................................................................................ 773
20.1.2 Block Diagram..................................................................................................... 774
20.2 Register Descriptions ........................................................................................................ 776
20.2.1 Access to UBC Control Registers ........................................................................ 776
20.2.2 Break Address Register A (BARA) ..................................................................... 777
20.2.3 Break ASID Register A (BASRA)....................................................................... 778
20.2.4 Break Address Mask Register A (BAMRA)........................................................ 778
20.2.5 Break Bus Cycle Register A (BBRA).................................................................. 779
20.2.6 Break Address Register B (BARB)...................................................................... 781
20.2.7 Break ASID Register B (BASRB) ....................................................................... 781
20.2.8 Break Address Mask Register B (BAMRB) ........................................................ 781
20.2.9 Break Data Register B (BDRB) ........................................................................... 781
20.2.10 Break Data Mask Register B (BDMRB).............................................................. 782
20.2.11 Break Bus Cycle Register B (BBRB) .................................................................. 783
20.2.12 Break Control Register (BRCR) .......................................................................... 783
20.3 Operation .......................................................................................................................... 785
20.3.1 Explanation of Terms Relating to Accesses......................................................... 785
20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 786
20.3.3 User Break Operation Sequence .......................................................................... 787
20.3.4 Instruction Access Cycle Break ........................................................................... 788
20.3.5 Operand Access Cycle Break............................................................................... 789
20.3.6 Condition Match Flag Setting .............................................................................. 790
20.3.7 Program Counter (PC) Value Saved .................................................................... 790
20.3.8 Contiguous A and B Settings for Sequential Conditions ..................................... 791
20.3.9 Usage Notes ......................................................................................................... 792
20.4 User Break Debug Support Function ................................................................................ 793
20.5 Examples of Use ............................................................................................................... 795
20.6 User Break Controller Stop Function................................................................................ 797
20.6.1 Transition to User Break Controller Stopped State.............................................. 797
20.6.2 Cancelling the User Break Controller Stopped State ........................................... 797
20.6.3 Examples of Stopping and Restarting the User Break Controller........................ 798
Section 21 Hitachi User Debug Interface (H-UDI)
21.1 Overview........................................................................................................................... 799
21.1.1 Features................................................................................................................ 799
Rev. 6.0, 07/02, page xxxii of I
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