Hitachi SH7750 Hardware Manual page 1000

CKIO2ENB CKIO2ENB
CKIO2ENB CKIO2ENB
Description
RD2, RD/WR2, and CKIO2 have the same pin states as RD, RD/WR, and
0
CKIO, respectively
RD2, RD/WR2, and CKIO2 are in the high-impedance state
1
Note: CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases.
However, CKIO2 is not fed back.
Rev. 6.0, 07/02, page 950 of 986