Hitachi SH7750 Hardware Manual page 87

Table 1.4 Pin Functions (cont)
Pin
No. No. Pin Name
176 F16 MD0/SCK
177 C15 MD1/TXD2 I/O
178 E15 MD2/RXD2 I
179 D15 IRL0
180 D17 IRL1
IRL2
181 A17
IRL3
182 B17
183 C16 NMI
184 A15 XTAL2
185 A16 EXTAL2
186 A14 VSS-RTC
187 C14 VDD-RTC
188 B13 CA
189 C13 VDDQ
190 D13 CTS2
191 A13 TCLK
192 D12 MD8/RTS2 I/O
193 C12 VDDQ
194 D14 VSSQ
195 B12 MD7/TXD
196 E12 SCK2/
MRESET
197 A12 VDD
I/O Function
I/O Mode/SCI1
clock
Mode/SCIF
data output
Mode/SCIF
data input
I Interrupt 0
I Interrupt 1
I Interrupt 2
I Interrupt 3
I Nonmaskable
interrupt
O RTC crystal
resonator pin
I RTC crystal
resonator pin
Power RTC GND
(0 V)
Power RTC VDD
(3.3 V)
I Hardware
standby request
Power IO VDD (3.3 V)
I/O SCIF data control
(CTS)
I/O RTC/TMU
clock
Mode/SCIF data
control (RTS)
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Mode/SCI1 data
output
I SCIF clock/
manual reset
Power Internal VDD
(1.5 V)
Reset SRAM DRAM
MD0 SCK SCK
MD1 TXD2 TXD2
MD2 RXD2 RXD2
RTS2 RTS2
MD8
MD7 TXD TXD
MRESET SCK2
SCK2
Memory Interface
SDRAM PCMCIA MPX
SCK SCK
TXD2 TXD2
RXD2 RXD2
RTS2 RTS2
TXD TXD
SCK2 SCK2
Rev. 6.0, 07/02, page 37 of 986
SCK
TXD2
RXD2
RTS2
TXD
SCK2