Table 9.1 Status Of Cpu And Peripheral Modules In Power-Down Modes - Hitachi SH7750 Hardware Manual

Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Power-
Down Entering
Mode Conditions CPG
Sleep SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR
Deep SLEEP
sleep instruction
executed
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Standby SLEEP
instruction
executed
while STBY
bit is 1 in
STBCR
Hardware Setting CA
standby pin low
(SH7750S,
SH7750R)
Module Setting
standby MSTP bit
to 1 in
STBCR/
STBCR2
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Rev. 6.0, 07/02, page 222 of 986
CPU
Operating Halted
(registers
held)
Operating Halted
(registers
held)
Halted Halted
(registers
held)
Halted Halted
Operating Operating Held
Status
On-chip
On-Chip Peripheral
Memory Modules
Held Operating
Held Operating
(DMA
halted)
Held Halted*
Undefined Halted*
Specified
modules
halted*
External
Pins Memory
Refreshing • Interrupt
Held
Held Self-
refreshing
Held Self-
refreshing
High Undefined
impedance
Refreshing • Clearing
Held
Exiting
Method
• Reset
• Interrupt
• Reset
• Interrupt
• Reset
• Power-on
reset
MSTP bit
to 0
• Reset