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Table 22.29 Clock and Control Signal Timing (HD6417750BP200M, HD6417750SBP200)
V
= 3.0 to 3.6 V, V
DDQ
Item
EXTAL
PLL2
clock input
operating
frequency
PLL2 not
operating
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width t
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock
PLL2 operating
output
PLL2 not operating
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
RESET assert time
PLL synchronization settling time
Rev. 6.0, 07/02, page 852 of 986
= 1.5 V, T
= –20 to +75°C, C
DD
a
Symbol
1/2 divider
f
operating
1/2 divider not
f
operating
1/2 divider
f
operating
1/2 divider not
f
operating
t
t
t
t
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
= 30 pF
L
Min
16
EX
8
EX
2
EX
1
EX
15
EXcyc
3.5
EXL
3.5
EXH
—
EXr
—
EXf
25
OP
1
OP
10
cyc
1
CKOL1
1
CKOH1
—
CKOr
—
CKOf
3
CKOL2
3
CKOH2
10
OSC1
10
OSCMD
20
SCK2RS
20
SCK2RH
3
MDRS
20
MDRH
20
RESW
200
PLL
Max
Unit
Figure
67
MHz
34
67
34
1000
ns
22.1
—
ns
22.1
—
ns
22.1
4
ns
22.1
4
ns
22.1
100
MHz
100
MHz
1000
ns
22.2(1)
—
ns
22.2(1)
—
ns
22.2(1)
3
ns
22.2(1)
3
ns
22.2(1)
—
ns
22.2(2)
—
ns
22.2(2)
—
ms
22.3, 22.5
—
ms
22.3, 22.5
—
ns
22.11
—
ns
22.3, 22.5, 22.11
—
t
22.12
cyc
—
ns
22.3, 22.5, 22.12
—
t
22.3, 22.4, 22.5,
cyc
22.6, 22.11
µs
—
22.9, 22.10
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