Operation In Asynchronous Mode - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine
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15.3.2

Operation in Asynchronous Mode

In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.5 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times
the length of one bit, so that the transfer data is latched at the center of each bit.
1
(LSB)
Serial
0
D0
data
Start
bit
1 bit
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SCSMR1 setting.
D1
D2
D3
D4
Transmit/receive data
7 or 8 bits
One unit of transfer data (character or frame)
Parity, Two Stop Bits)
(MSB)
D5
D6
D7
0/1
Parity
bit
1 bit,
or none
Rev. 6.0, 07/02, page 623 of 986
Idle state (mark state)
1
1
1
Stop
bit(s)
1 or
2 bits

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