Hitachi SH7750 Hardware Manual page 545

Table 14.3 DMAC Registers (cont)
Chan-
nel Name
1 DMA source
address register 1
DMA destination
address register 1
DMA transfer
count register 1
DMA channel
control register 1
DMA source
2
address register 2
DMA destination
address register 2
DMA transfer
count register 2
DMA channel
control register 2
3 DMA source
address register 3
DMA destination
address register 3
DMA transfer
count register 3
DMA channel
control register 3
Com- DMA operation
mon register
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
*1 Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
*2 In the SH7750, writes from the CPU are masked in DDT mode, while writes from
external I/O devices using the DTR format are possible. In the SH7750S, writes from
the CPU and writes from external I/O devices using the DTR format are possible In
DDT mode.
Abbre- Read/
viation Write
R/W
SAR1
R/W
DAR1
DMATCR1 R/W
1
R/W *
CHCR1
SAR2 R/W
DAR2 R/W
DMATCR2 R/W
1
R/W *
CHCR2
SAR3 R/W
DAR3 R/W
DMATCR3 R/W
1
R/W *
CHCR3
1
R/W *
DMAOR
Initial Value P4 Address
Undefined H'FFA00010 H'1FA00010 32
Undefined H'FFA00014 H'1FA00014 32
Undefined H'FFA00018 H'1FA00018 32
H'00000000 H'FFA0001C H'1FA0001C 32
Undefined H'FFA00020 H'1FA00020 32
Undefined H'FFA00024 H'1FA00024 32
Undefined H'FFA00028 H'1FA00028 32
H'00000000 H'FFA0002C H'1FA0002C 32
Undefined H'FFA00030 H'1FA00030 32
Undefined H'FFA00034 H'1FA00034 32
Undefined H'FFA00038 H'1FA00038 32
H'00000000 H'FFA0003C H'1FA0003C 32
H'00000000 H'FFA00040 H'1FA00040 32
Rev. 6.0, 07/02, page 495 of 986
Area 7 Access
Address Size