Ic Data Array; Figure 4.8 Memory-Mapped Ic Address Array - Hitachi SH7750 Hardware Manual

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other cases, no operation is performed. This operation is used to invalidate a specific IC entry.

If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an

interrupt is not generated, no operation is performed, and the write is not executed. If an

instruction TLB multiple hit exception occurs during address translation, processing switches

to the instruction TLB multiple hit exception handling routine.

Address field

1 1 1 1 0 0 0 0

: Validity bit

: Association bit

: Reserved bits (0 write value, undefined read value)

IC Data Array

The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data

array access requires a 32-bit address field specification (when reading or writing) and a 32-bit

data field specification. The entry to be accessed is specified in the address field, and the longword

data to be written is specified in the data field.

In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is

specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2]

are used for the longword data specification in the entry. As only longword access is used, 0

should be specified for address field bits [1:0].

The data field is used for the longword data specification.

The following two kinds of operation can be used on the IC data array:

1. IC data array read

Longword data is read into the data field from the data specified by the longword specification

bits in the address field in the IC entry corresponding to the entry set in the address field.

2. IC data array write

The longword data specified in the data field is written for the data specified by the longword

specification bits in the address field in the IC entry corresponding to the entry set in the

address field.

Rev. 6.0, 07/02, page 113 of 986

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