Hitachi SH7750 Hardware Manual page 598

• TDACK TDACK: Reply strobe signal for external device from DMAC TDACK TDACK
The assert timing of this signal is the same as the DACKn assert timing of the memory
interfaces.
Note that it is a low active signal.
• ID1, ID0: Channel number notification signals
 00: Channel 0 (means demand data transfer)
 01: Channel 1
 10: Channel 2
 11: Channel 3
Data Transfer Request Format
63 61 60 59 57
SZ ID MD
R/W
The data transfer request format (DTR format) consists of 64 bits, with connection to D[63:0]. In
the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol
using the data bus, the transfer data size, read/write access, channel number, transfer request
mode, number of transfers, and transfer source or transfer destination address are specified. A
specification in bits 47–32 is invalid.
In the SH7750, only single address mode can be set in normal data transfer mode (channel 0).
With the DTR format, DS = (0: MD = 10, 11, 1: MD = 01), RL = 0, AL = 0, DM[1:0] = 01,
SM[1:0] = 01, RS[3:0] = (0010: R/W = 0, 0011: R/W = 1), TM = (0: MD = 11, 1: MD = 01, 10),
TS[2:0] = (SZ), and IE = 0 settings are made in DMA channel control register 0, COUNT is set in
transfer count register 0, and ADDRESS is set in source/destination address register 0. Therefore,
in DDT mode, the above control registers cannot be written to by the CPU, but can be read.
In the SH7750S, DMAC control registers CHCR0, SAR0, DAR0, and DMATCR0 can be written
to and read by the CPU even in normal data transfer mode (channel 0). Caution is necessary in this
case, as a DMAC control register written to by the CPU will be overwritten by a subsequent
transfer request (MD[1:0] = 01, 10, or 11) using the DTR format.
Bits 63 to 61: Transmit Size (SZ2–SZ0)
• 000: Byte size (8-bit) specification
• 001: Word size (16-bit) specification
• 010: Longword size (32-bit) specification
Rev. 6.0, 07/02, page 548 of 986
55 48
COUNT
Figure 14.25 Data Transfer Request Format
31
(Reserved) ADDRESS
0