Hitachi SH7750 Hardware Manual page 36

Figure 11.4 Example of Use of Alarm Function ................................................................. 288
Figure 11.5 Example of Crystal Oscillator Circuit Connection .......................................... 290
Figure 12.1 Block Diagram of TMU................................................................................... 292
Figure 12.2 Example of Count Operation Setting Procedure .............................................. 305
Figure 12.3 TCNT Auto-Reload Operation......................................................................... 305
Figure 12.4 Count Timing when Operating on Internal Clock............................................ 306
Figure 12.5 Count Timing when Operating on External Clock........................................... 306
Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock ..................... 307
Figure 12.7 Operation Timing when Using Input Capture Function................................... 308
Figure 13.1 Block Diagram of BSC .................................................................................... 313
Figure 13.2 Correspondence between Virtual Address Space and External Memory
Space................................................................................................................ 319
Figure 13.3 External Memory Space Allocation ................................................................. 321
Example of RDY Sampling Timing at which BCR4 is Set
Figure 13.4
(Two Wait Cycles are Inserted by WCR2) ...................................................... 338
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR .......................................... 370
Figure 13.6 Basic Timing of SRAM Interface .................................................................... 388
Figure 13.7 Example of 64-Bit Data Width SRAM Connection......................................... 389
Figure 13.8 Example of 32-Bit Data Width SRAM Connection......................................... 390
Figure 13.9 Example of 16-Bit Data Width SRAM Connection......................................... 391
Figure 13.10 Example of 8-Bit Data Width SRAM Connection........................................... 392
Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) ...................................... 393
SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal).... 394
Figure 13.12
Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) 395
Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3)......................... 396
Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3)......................... 397
Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3).............. 398
Figure 13.17 Basic DRAM Access Timing........................................................................... 400
Figure 13.18 DRAM Wait State Timing ............................................................................... 401
Figure 13.19 DRAM Burst Access Timing ........................................................................... 402
Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) ..................... 403
Figure 13.21 Burst Access Timing in DRAM EDO Mode ................................................... 404
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0) ............................................................ 405
Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, AnW = 0) ............................................................ 406
Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start
(EDO Mode, RCD = 0, AnW = 0) ................................................................... 407
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0) ................................................................... 408
Figure 13.23 CAS-Before-RAS Refresh Operation .............................................................. 409
Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) ....... 410
Figure 13.25 DRAM Self-Refresh Cycle Timing ................................................................. 412
Rev. 6.0, 07/02, page xxxvi of I