Hitachi SH7750 Hardware Manual page 367

Table 13.1 BSC Pins (cont)
Name Signals
RD2
Read/column
address strobe/
cycle frame 2
Read/write 2 RD/WR2
Notes: *1 MD3/CE2A input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
*2 MD4/CE2B input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
*3 MD5/RAS2 input/output switching is performed by BCR1.DRAMTP. Output is selected
when BCR1.DRAMTP (2–0) = 101.
*4 In a power-on reset by means of the RESET pin.
I/O Description
Same signal as RD/CASS/FRAME
O
This signal is used when the RD/CASS/FRAME
signal load is heavy.
O Same signal as RD/WR
This signal is used when the RD/WR signal load is
heavy.
Rev. 6.0, 07/02, page 317 of 986