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Table E.1
Pin States in Reset, Power-Down State, and Bus-Released State (cont)
Signal Name
I/O
RD2 *
10
O
RD/WR2 *
10
O
CKIO2ENB
I
CA
I
Notes: I: Input
O: Output
H: High-level output
L: Low-level output
Z: High-impedance
K: Output state held
*1 Output when area 2 DRAM is used.
*2 Output when area 5 PCMCIA is used.
*3 Output when area 6 PCMCIA is used.
*4 Depends on refresh and DMAC operations.
*5 Z (I) or O (refresh), depending on register setting (BCR1.HIZCNT).
*6 Depends on refresh operation.
*7 Z (I) or H (state held), depending on register setting (BCR1.HIZMEM).
*8 Z or O, depending on register setting (STBCR.PHZ).
*9 Output when refreshing is set.
*10 Operation in respective state when CKIO2ENB = 0; Z when CKIO2ENB = 1.
*11 Z or O, depending on register setting (FRQCR.CKOEN).
*12 Pulled up or not pulled up, depending on register setting (STBCR.PPU).
*13 Pulled up or not pulled up, depending on register setting (BCR1.IPUP).
*14 Pulled up or not pulled up, depending on register setting (BCR1.OPUP).
*15 Not pulled up.
*16 Pulled up with a built-in pull-up resistance. However, cannot be used for MD pin pull-
up in a power-on reset. Pull up or down outside the SH-4.
*17 Output when refreshing is set (SH7750R only).
*18 Z or O, depending on register setting (STBCR2.STHZ) (SH7750R only).
Reset
(Power-On)
Master Slave
Master Slave
16
Z *
O *
H
Z *
16
H
H
I
I
I
I
I
I
Reset
(Manual)
Standby
6
14
14
5
Z *
Z *
O *
Z *
14
Z *
14
H *
7
I
I
I
I
Rev. 6.0, 07/02, page 953 of 986
Hard-
Bus
ware
Released
Standby Notes
14
5
Z *
O *
Z
Z *
14
Z
I
I
I
I
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