Data Register (Sddr); Bypass Register (Sdbpr) - Hitachi SH7750 Hardware Manual

21.2.2

Data Register (SDDR)

The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and
SDDRL, that can be read and written to by the CPU. The value in this register is not initialized by
a TRST or CPU reset.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: *: Undefined
Bits 31 to 0—DR Data: These bits store the SDDR value.
21.2.3

Bypass Register (SDBPR)

The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When
bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the
H-UDI.
31 30 29
* *
R/W R/W R/W
23 22 21
* *
R/W R/W R/W
15 14 13
* *
R/W R/W R/W
7 6
* *
R/W R/W R/W
28 27
* * *
R/W R/W
20 19
* * *
R/W R/W
12 11
* * *
R/W R/W
5 4 3
* * *
R/W R/W
26 25
* *
R/W R/W
18 17
* *
R/W R/W
10 9
* *
R/W R/W
2 1
* *
R/W R/W
Rev. 6.0, 07/02, page 805 of 986
24
*
R/W
16
*
R/W
8
*
R/W
0
*
R/W