Hitachi SH7750 Hardware Manual page 12

Section
13.3.7 PCMCIA Interface
13.3.8 MPX Interface
13.3.9 Byte Control SRAM
Interface
13.3.10 Waits between
Access Cycles
13.3.11 Bus Arbitration
13.3.16 Notes on Usage
14.1 Overview
14.1.1 Features
14.1.2 Block Diagram
(SH7750, SH7750S)
14.2 Register Descriptions
(SH7750, SH7750S)
Rev. 6.0, 07/02, page xii of I
Page Item
444, 445
446 Table 13.18 Relationship
between Address and CE
when Using PCMCIA
Interface
449, 452 Figures 13.50, 13.53 to 13.55 Notes added
to 454
450 Figure 13.51 Wait Timing for
PCMCIA Memory Card
Interface
451 Figure 13.52 PCMCIA Space
Allocation
455
471 Figure 13.71 MPX Interface
Timing 7
457 to 472 Figures 13.57 to 13.72
473
475 to 477 Figures 13.74 to 13.76
479 Figure 13.77 Waits between
Access Cycles
480, 481
487 Refresh, Bus Arbitration
487 Synchronous DRAM Mode
Register Setting (SH7750,
SH7750R Only)
489
489 to 491
492
492 Figure 14.1 Block Diagram
of DMAC
496
Description
Description amended
and added
Table amended
SH7750R added to
Note
Amended
Description added and
amended
Amended
Notes added
Description amended
Notes added
Replaced
Description added and
amended
Description amended
Newly added
Description added and
amended
Description amended
Title amended
Amended
Title amended