Hitachi SH7751 Hardware Manual

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Summary of Contents for Hitachi SH7751

Page 1 DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark,...
Page 2 Hitachi SuperH RISC engine SH7751 Series SH7751, SH7751R Hardware Manual ADE-602-201B Rev. 3.0 4/11/2002 Hitachi, Ltd.
Page 3 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7751 Series is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and PCI controller (PCIC).
Page 5 User manuals for SH7751 and SH7751R Name of Document Document No. SH7751 Series Hardware Manual This manual SH-4 Programming Manual ADE-602-156 User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual...
Page 6: Table Of Contents
Contents Section 1 Overview ......................SH7751 Series Features..................... Block Diagram ........................10 Pin Arrangement ....................... 11 Pin Functions........................13 1.4.1 Pin Functions (256-Pin QFP) ................13 1.4.2 Pin Functions (256-Pin BGA) ................24 Section 2 Programming Model ..................35 Data Formats ........................35 Register Configuration ......................
Page 7 3.4.2 Instruction TLB (ITLB) Configuration ..............69 3.4.3 Address Translation Method ................69 MMU Functions ........................ 72 3.5.1 MMU Hardware Management ................72 3.5.2 MMU Software Management................72 3.5.3 MMU Instruction (LDTLB) ................. 72 3.5.4 Hardware ITLB Miss Handling................73 3.5.5 Avoiding Synonym Problems ................
Page 8 Memory-Mapped Cache Configuration (SH7751) ............103 4.5.1 IC Address Array ....................103 4.5.2 IC Data Array ....................... 104 4.5.3 OC Address Array ....................105 4.5.4 OC Data Array ..................... 106 Memory-Mapped Cache Configuration (SH7751R) ............107 4.6.1 IC Address Array ....................108 4.6.2...
Page 9 Data Formats ........................155 6.2.1 Floating-Point Format ..................155 6.2.2 Non-Numbers (NaN).................... 157 6.2.3 Denormalized Numbers..................158 Registers ..........................159 6.3.1 Floating-Point Registers ..................159 6.3.2 Floating-Point Status/Control Register (FPSCR) ..........161 6.3.3 Floating-Point Communication Register (FPUL)..........162 Rounding ........................... 162 Floating-Point Exceptions ....................
Page 10 9.5.1 Transition to Pin Sleep Mode................225 9.5.2 Exit from Pin Sleep Mode ..................225 Standby Mode ........................225 9.6.1 Transition to Standby Mode ................. 225 9.6.2 Exit from Standby Mode ..................226 9.6.3 Clock Pause Function................... 227 Module Standby Function ....................227 9.7.1 Transition to Module Standby Function...............
Page 11 10.8.3 Notes on Register Access ..................257 10.9 Using the WDT ......................... 258 10.9.1 Standby Clearing Procedure................. 258 10.9.2 Frequency Changing Procedure ................258 10.9.3 Using Watchdog Timer Mode................259 10.9.4 Using Interval Timer Mode.................. 259 10.10 Notes on Board Design...................... 260 Section 11 Realtime Clock (RTC) ..................
Page 12 Section 12 Timer Unit (TMU) ..................287 12.1 Overview ........................... 287 12.1.1 Features ........................ 287 12.1.2 Block Diagram ..................... 288 12.1.3 Pin Configuration ....................288 12.1.4 Register Configuration ..................289 12.2 Register Descriptions......................290 12.2.1 Timer Output Control Register (TOCR) .............. 290 12.2.2 Timer Start Register (TSTR) ................
Page 13 .......... 463 14.1 Overview ........................... 463 14.1.1 Features ........................ 463 14.1.2 Block Diagram (SH7751)..................466 14.1.3 Pin Configuration (SH7751) ................467 14.1.4 Register Configuration (SH7751) ................ 468 14.2 Register Descriptions......................470 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........... 470 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) ........471 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......
Page 14 14.4.1 Examples of Transfer between External Memory and an External Device with DACK ......................519 14.5 On-Demand Data Transfer Mode (DDT Mode) ..............520 14.5.1 Operation......................520 14.5.2 Pins in DDT Mode ....................522 14.5.3 Transfer Request Acceptance on Each Channel........... 525 14.5.4 Notes on Use of DDT Module ................
Page 15 15.3.2 Operation in Asynchronous Mode................ 599 15.3.3 Multiprocessor Communication Function ............609 15.3.4 Operation in Synchronous Mode................618 15.4 SCI Interrupt Sources and DMAC..................627 15.5 Usage Notes........................628 Section 16 Serial Communication Interface with FIFO (SCIF) ......633 16.1 Overview ........................... 633 16.1.1 Features ........................
Page 16 17.3.1 Overview ......................686 17.3.2 Pin Connections....................687 17.3.3 Data Format......................688 17.3.4 Register Settings....................689 17.3.5 Clock ........................691 17.3.6 Data Transfer Operations ..................694 17.4 Usage Notes........................701 Section 18 I/O Ports ......................707 18.1 Overview ........................... 707 18.1.1 Features ........................
Page 17 20.6.1 Transition to User Break Controller Stopped State ..........775 20.6.2 Cancelling the User Break Controller Stopped State ........... 775 20.6.3 Examples of Stopping and Restarting the User Break Controller ......776 Section 21 Hitachi User Debug Interface (H-UDI) ............ 777 21.1 Overview ........................... 777 21.1.1 Features ........................
Page 18 21.1.3 Pin Configuration ....................779 21.1.4 Register Configuration ..................780 21.2 Register Descriptions......................781 21.2.1 Instruction Register (SDIR).................. 781 21.2.2 Data Register (SDDR)..................782 21.2.3 Bypass Register (SDBPR)..................782 21.2.4 Interrupt Factor Register (SDINT) ............... 783 21.2.5 Boundary Scan Register (SDBSR) ............... 783 21.3 Operation...........................
Page 19 22.2.21 PCI Interrupt Mask Register (PCIINTM)............. 848 22.2.22 PCI Address Data Register at Error (PCIALR)............ 850 22.2.23 PCI Command Data Register at Error (PCICLR)..........851 22.2.24 PCI Arbiter Interrupt Register (PCIAINT)............853 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM) ..........855 22.2.26 PCI Error Bus Master Data Register (PCIBMLR) ..........
Page 20 22.6.2 Interrupts from External PCI Devices ..............921 22.6.3 ........................921 22.7 Error Detection ........................922 22.8 PCIC Clock ........................922 22.9 Power Management......................923 22.9.1 Power Management Overview ................923 22.9.2 Stopping the Clock ....................924 22.9.3 Compatibility with Standby and Sleep ..............927 22.10 Port Functions ........................
Page 21 Figures Figure 1.1 Block Diagram of SH7751 Series Functions ........... Figure 1.2 Pin Arrangement (256-Pin QFP)..............Figure 1.3 Pin Arrangement (256-Pin BGA) ..............Figure 2.1 Data Formats....................Figure 2.2 CPU Register Configuration in Each Processor Mode ........Figure 2.3 General Registers .....................
Page 22 Timing When Power Other than VDD-RTC is Off ......... 239 Figure 9.15 Timing When VDD-RTC Power is Off On ..........240 Figure 10.1(1) Block Diagram of CPG (SH7751) ..............243 Figure 10.1(2) Block Diagram of CPG (SH7751R)..............244 Figure 10.2 Block Diagram of WDT................... 253 Figure 10.3...
Page 23 Figure 12.7 Operation Timing when Using Input Capture Function........302 Figure 13.1 Block Diagram of BSC ..................307 Figure 13.2 Correspondence between Virtual Address Space and External Memory Space 311 Figure 13.3 External Memory Space Allocation ..............313 Figure 13.4 Example of Sampling Timing at which BCR4 is Set (Two Wait Cycles are Inserted by WCR2) ............
Page 24 Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle ..................... 410 Figure 13.35 Auto-Refresh Operation................... 411 Figure 13.36 Synchronous DRAM Auto-Refresh Timing ............ 412 Figure 13.37 Synchronous DRAM Self-Refresh Timing ............413 Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL) ......... 415 Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ....
Page 25 Figure 13.62 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................445 Figure 13.63 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................
Page 26 Figure 14.15 Dual Address Mode/Burst Mode External Bus External Bus/ (Edge Detection), DACK (Read Cycle) ..........508 Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) External Bus..................... 509 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus On-Chip SCI (Level Detection) .....................
Page 27 Figure 14.40 Write to Synchronous DRAM (Row Hit) ............536 Figure 14.41 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ........537 Figure 14.42 DDT Mode Setting................... 538 Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device External Bus Data Transfer................
Page 28 Figure 15.10 Sample Serial Reception Flowchart (1) ............606 Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ....................609 Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)........610 Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart........
Page 29 Figure 17.7 Sample Initialization Flowchart ............... 695 Figure 17.8 Sample Transmission Processing Flowchart............ 697 Figure 17.9 Sample Reception Processing Flowchart ............699 Figure 17.10 Receive Data Sampling Timing in Smart Card Mode........701 Figure 17.11 Retransfer Operation in SCI Receive Mode............. 702 Figure 17.12 Retransfer Operation in SCI Transmit Mode ...........
Page 30 Figure 22.19 Endian Control for Local Bus ................912 Figure 22.20 Data Alignment at DMA Transfer ..............913 Figure 22.21(1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) .... 915 Figure 22.21(2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus)..916 Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) .
Page 31 Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) ...... 981 Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)......982 Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD [1:0] = 01, TRWL [2:0] = 010)............
Page 32 Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001, TRC [2:0] = 001) ............. 1004 Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001)......1005 Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait........................
Page 33 Figure 23.67 H-UDI Data Transfer Timing ................1021 Figure 23.68 Pin Break Timing..................... 1021 Figure 23.69 NMI Input Timing ................... 1022 Figure 23.70 PCI Clock Input Timing................... 1025 Figure 23.71 Output Signal Timing ..................1025 Figure 23.72 Output Signal Timing ..................1026 Figure 23.73 I/O Port Input/Output Timing ................
Page 34 State of Registers in Standby Mode ..............226 Table 10.1 CPG Pins ......................246 Table 10.2 CPG Register...................... 246 Table 10.3(1) Clock Operating Modes (SH7751)..............247 Table 10.3(2) Clock Operating Modes (SH7751R) ..............247 Table 10.4 FRQCR Settings and Internal Clock Frequencies ..........248 Table 10.5 WDT Registers....................
Page 35 Table 13.14 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing 379 Table 13.15 Example of Correspondence between SH7751 Series and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0) ..395 Table 13.16 Cycles in Which Pipelined Access Can Be Used ..........409 Table 13.17...
Page 36 Table 15.2 SCI Registers...................... 572 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ..... 591 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode....594 Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)..................
Page 37 Table 21.3 Structure of Boundary Scan Register ..............784 Table 22.1 Pin Configuration ....................804 Table 22.2 List of PCI Configuration Registers ..............806 Table 22.3 PCI Configuration Register Configuration............807 Table 22.4 List of PCIC Local Registers................808 Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)......
Page 38 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) ................... 1027 Table A.1 Address List......................1031 Table C.1 Clock Operating Modes (SH7751)..............1041 Table C.2 Clock Operating Modes (SH7751R) ..............1041 Table C.3 Area 0 Memory Map and Bus Width ..............1042 Table C.4...
Page 39 Rev. 3.0, 04/02, page xxxviii of xxxviii...
Page 40: Section 1 Overview
50% reduction in program size over a 32-bit instruction set. The SH7751 Series feature the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751 Series have an instruction cache, an...
Page 41: Figure 13.61 Mpx Interface Timing
Table 1.1 SH7751 Series Features Item Features Operating frequency: 240 MHz* /200 MHz* /167 MHz* /133 MHz* Performance: 430 MIPS (240 MHz), 360 MIPS (200 MHz) 300 MIPS (167 MHz), 240 MIPS (133 MHz) 1.2 GFLOPS (167 MHz), 0.93 GFLOPS (133 MHz) 1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz)
Page 42 Table 1.1 SH7751 Series Features (cont) Item Features Original Hitachi SuperH architecture 32-bit internal data bus General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers RISC-type instruction set (upward-compatible with SuperH Series)
Page 43 Table 1.1 SH7751 Series Features (cont) Item Features On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt...
Page 44 Clock pulse Choice of main clock generator (CPG) SH7751: 1/2, 1, 3, or 6 times EXTAL SH7751R: 1, 6, or 12 times EXTAL Clock modes: (Maximum frequency: Varies with models) CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock...
Page 45 [SH7751R] 16 kbytes, 2-way set associative 256 entries/way, 32-byte block length Cache-double-mode (16-kbyte cache) Index mode SH7751-compatible mode (8 kbytes, direct mapping) Operand cache (OC) 32 kbytes, 2-way set associative 512 entries/way, 32-byte block length Cache-double-mode (32-kbyte cache) Index mode...
Page 46 Table 1.1 SH7751 Series Features (cont) Item Features Interrupt controller Five independent external interrupts (NMI, IRL3 to IRL0) (INTC) 15-level signed external interrupts: IRL3 to IRL0 On-chip peripheral module interrupts: Priority level can be set for each module User break...
Page 47 Table 1.1 SH7751 Series Features (cont) Item Features Direct memory Physical address DMA controller access controller SH7751: 4-channel (DMAC) SH7751R: 8-channel Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes Address modes: 1-bus-cycle single address mode 2-bus-cycle dual address mode...
Page 48 Table 1.1 SH7751 Series Features (cont) Item Features PCI bus controller PCI bus controller (Rev.2.1-compatible)* (PCIC) 32-bit bus 33 MHz/66 MHz support PCI master/slave support PCI host function support Built-in bus arbiter 4 built-in PCI-dedicated DMAC (direct memory access controller)
Page 49: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram of the SH7751 Series. Lower 32-bit data Cache and I cache ITLB UTLB O cache controller INTC DMAC (SCIF) PCIC (PCI)DMAC BSC: Bus state controller CPG: Clock pulse generator DMAC: Direct memory access controller...
Page 50: Pin Arrangement
Pin Arrangement XTAL2 EXTAL2 VDD-RTC VSS-RTC PCICLK IDSEL /MD9 /MD10 MD6/ MD2/RXD2 QFP256 TCLK MD8/ MD1/TXD2 MD0/SCK2 MD7/ (Top view) AUDSYNC AUDCK AUDATA0 AUDATA1 AUDATA2 AUDATA3 Reserved MD3/ MD4/ VDD (internal) DACK0 VSS (internal) DACK1 DRAK0 DRAK1 VDDQ (IO) STATUS0 VSSQ (IO) STATUS1 /BRKACK...
Page 51: Figure 1.3 Pin Arrangement (256-Pin Bga)
BGA256 (Top view) VDDQ(IO) VSS (internal) VDD-CPG/RTC VSSQ(IO) VSS-CPG/RTC VDD-PLL1/2 VDD (internal) VSS-PLL1/2 Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * May be connected to V Figure 1.3 Pin Arrangement (256-Pin BGA) Rev.
Page 52: Pin Functions
Pin Functions 1.4.1 Pin Functions (256-Pin QFP) Table 1.2 Pin Functions Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND Data in (H-UDI) Chip select 0 Chip select 1 Chip select 4 ...
Page 53 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data D7–D0 DQM0 DQM0 select signal D15–D8...
Page 54 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND Address Address Address Address...
Page 55 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD Power Internal GND Address 100 A19 Address...
Page 56 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus grant (host function) Bus request (host function) Bus request MD10 MD10 (host function)/ mode 119 VDDQ Power IO VDD 120 VSSQ Power IO GND ...
Page 57 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 134 AD28 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 135 AD27 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 136 AD26 PCI address/ (Port) (Port) (Port)
Page 58 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Device select 157 VDDQ Power IO VDD 158 VSSQ Power IO GND Transaction stop Exclusive access Parity error 162 PAR Parity 163 C/ Command/...
Page 59 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 179 AD5 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 180 AD4 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 181 AD3 PCI address/ (Port) (Port) (Port)
Page 60 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX acknowledge/ bus request request/bus acknowledge 204 MD6/ Mode/ (PCMCIA) Bus ready 206 TXD SCI data output 207 VDDQ Power IO VDD 208 VSSQ...
Page 61 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 225 VDD Power Internal VDD 226 VSS Power Internal GND 227 AUDATA2 AUD data 228 AUDATA3 AUD data 229 Reserved Do not connect 230 MD3/...
Page 62 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 247 VDDQ Power IO VDD 248 VSSQ Power IO GND 249 VDD-PLL2 Power PLL2 VDD 250 VSS-PLL2 Power PLL2 GND 251 VDD-PLL1 Power PLL1 VDD 252 VSS-PLL1 Power PLL1 GND 253 VDD-CPG...
Page 63: Pin Functions (256-Pin Bga)
1.4.2 Pin Functions (256-Pin BGA) Table 1.3 Pin Functions Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND Data in (H-UDI) Chip select 0 Chip select 1 Chip select 4 Chip select 5...
Page 64 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data D7–D0 DQM0 DQM0 select signal D15–D8 DQM1 DQM1 select signal...
Page 65 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND Address Address Address Address ...
Page 66 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD Power Internal GND Address Address Address...
Page 67 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Bus grant (host function) Bus request (host function) Bus request MD10 MD10 (host function)/ mode VDDQ Power IO VDD VSSQ Power IO GND Bus request...
Page 68 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AD26 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD25 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD24 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port...
Page 69 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Transaction stop Exclusive access Parity error Parity Command/ byte enable AD15 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD14...
Page 70 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port VDDQ Power I/O VDD...
Page 71 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA request/bus acknowledge MD6/ Mode/ (PCMCIA) Bus ready SCI data output VDDQ Power IO VDD VSSQ Power IO GND Power Internal VDD Power Internal GND...
Page 72 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AUDATA2 AUD data AUDATA3 AUD data Do not connect MD3/ Mode/ PCMCIA-CE MD4/ Mode/ PCMCIA-CE Mode VDDQ Power IO VDD VSSQ Power IO GND...
Page 73 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSS-PLL2 Power PLL2 GND VDD-PLL1 Power PLL1 VDD VSS-PLL1 Power PLL1 GND VDD-CPG Power CPG VDD VSS-CPG Power CPG GND XTAL Crystal resonator EXTAL External input clock/crystal resonator...
Page 74: Section 2 Programming Model
Section 2 Programming Model Data Formats The data formats handled by the SH7751 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 75: Register Configuration
Processor Modes: The SH7751 Series has two processor modes, user mode and privileged mode. The SH7751 Series normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be...
Page 76: Table 2.1 Initial Register Values
Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.
Page 77: Figure 2.2 Cpu Register Configuration In Each Processor Mode
R0 _ BANK0* R0 _ BANK1* R0 _ BANK0* R1 _ BANK0* R1 _ BANK0* R1 _ BANK1* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK1* R3 _ BANK0* R4 _ BANK0* R4 _ BANK0* R4 _ BANK1* R5 _ BANK0* R5 _ BANK1*...
Page 78: General Registers
R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7751 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
Page 79: Figure 2.3 General Registers
SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...
Page 80: Floating-Point Registers
2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Page 81: Figure 2.4 Floating-Point Registers
Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0...
Page 82: Control Registers
Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X = undefined)) 31 30 29 28 27 16 15 14 —...
Page 83: System Registers
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 84 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15;...
Page 85: Memory-Mapped Registers
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 86: Data Format In Registers
Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Longword Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.
Page 87: Processor States
Note: The SH7751 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. Processor States The SH7751 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state.
Page 88: Processor Modes
From any state when From any state when RESET = 0 RESET = 1 and MRESET = 0 Power-on reset state Manual reset state RESET = 0 Reset state RESET = 1 RESET = 1, MRESET = 1 Exception-handling state Bus request Bus request clearance...
Page 89 Rev. 3.0, 04/02, page 50 of 1064...
Page 90: Memory Management Unit (Mmu)
(translation lookaside buffer: TLB). The SH7751 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte).
Page 91 (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7751 Series is referred to as virtual address space, and the address space in physical memory as physical address space.
Page 92: Figure 3.1 Role Of The Mmu
Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev. 3.0, 04/02, page 53 of 1064...
Page 93: Register Configuration
3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Name tion Value* Address* Address* Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register Page table entry low PTEL Undefined H'FF00 0004 H'1F00 0004 32...
Page 94: Register Descriptions
Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.
Page 95 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware.
Page 96 Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction.
Page 97: Address Space
3.3.1 Physical Address Space The SH7751 Series supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3.
Page 98: Figure 3.3 Physical Address Space (Mmucr.at = 0)
P4 Area: The P4 area is mapped onto SH7751 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4.
Page 99: Figure 3.4 P4 Area
H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000 Operand cache data array H'F600 0000...
Page 100: External Memory Space
3.3.2 External Memory Space The SH7751 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC).
Page 101: Virtual Address Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in the SH7751 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1- Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.
Page 102: On-Chip Ram Space
3.3.4 On-Chip RAM Space In the SH7751 Series, half of the operand cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0, U0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area.
Page 103: Single Virtual Memory Mode And Multiple Virtual Memory Mode
Notes: (1) In single virtual memory mode of the SH7751 Series, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously.
Page 104: Tlb Functions
UTLB with a different ASID and unshared address translation information. Note that this restriction does not apply to the SH7751R. TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1.
Page 105: Figure 3.8 Relationship Between Page Size And Address Format
• 1-kbyte page Virtual address Physical address 10 9 10 9 Offset Offset • 4-kbyte page Virtual address Physical address 12 11 12 11 Offset Offset • 64-kbyte page Virtual address Physical address 16 15 16 15 Offset Offset • 1-Mbyte page Virtual address Physical address 20 19...
Page 106 SZ: Page size bits Specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-Mbyte page V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset.
Page 107 D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0.
Page 108: Instruction Tlb (Itlb) Configuration
3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries.
Page 109: Figure 3.10 Flowchart Of Memory Access Using Utlb
Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match...
Page 110: Figure 3.11 Flowchart Of Memory Access Using Itlb
Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match VPNs match...
Page 111: Mmu Functions
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7751 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.
Page 112: Hardware Itlb Miss Handling
3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7751 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB.
Page 113: Avoiding Synonym Problems
This problem does not occur with the instruction TLB or instruction cache. In the SH7751 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4- kbyte page, are subject to address translation.
Page 114: Mmu Exceptions
MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 115: Instruction Tlb Protection Violation Exception
Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3.
Page 116: Data Tlb Multiple Hit Exception
Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3.
Page 117: Data Tlb Miss Exception
3.6.5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1.
Page 118: Data Tlb Protection Violation Exception
3.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below.
Page 119: Memory-Mapped Tlb Configuration
3. Sets exception code H'080 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC.
Page 120: Itlb Address Array
performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 121: Itlb Data Array 1
3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.
Page 122: Itlb Data Array 2
3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 123: Figure 3.16 Memory-Mapped Utlb Address Array
In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0].
Page 124: Utlb Data Array 1
3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field.
Page 125: Utlb Data Array 2
3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 126: Section 4 Caches
RAM. When the EMODE bit in the CCR register is cleared to 0 in the SH7751R, both the IC and OC are set to SH7751 compatible mode. Operation is as shown in table 4.1. When the EMODE bit in the CCR register is set to 1, the cache characteristics are as shown in table 4.2.
Page 127: Register Configuration
Table 4.2 Cache Features (SH7751R) Item Instruction Cache Operand Cache Capacity 16-kbyte cache 32-kbyte cache or 16-kbyte cache + 16-kbyte RAM Type 2-way set-associative 2-way set-associative Line size 32 bytes 32 bytes Entries 256 entry/way 512 entry/way Write method Copy-back/write-through selectable Replace method LRU (Least Recently Used) LRU (Least Recently Used)
Page 128: Register Descriptions
0 must be specified in a write; the read value is 0. Figure 4.1 Cache and Store Queue Control Registers (CCR) (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: Cache-double-mode (SH7751R only. Reserved bit in SH7751.) IIX: IC index enable...
Page 129 EMODE: Cache-double-mode bit Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in the SH7751. The EMODE bit cannot be modified while the cache is in use. 0: SH7751-compatible-mode (Initial value) 1: Cache-double-mode Note: *1 Address allocation in OC index mode and RAM mode is not compatible with that in RAM mode.
Page 130: Operand Cache (Oc)
4.3.1 Configuration The operand cache in the SH7751 adopts the direct-mapping method, and consists of 512 cache lines. Each cache line is composed of a 19-bit tag, V bit, U bit, and 32-byte data. The operand cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 512 cache lines.
Page 131: Figure 4.2 Configuration Of Operand Cache (Sh7751)
1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Write data Read data Hit signal Figure 4.2 Configuration of Operand Cache (SH7751) Rev. 3.0, 04/02, page 92 of 1064...
Page 132: Figure 4.3 Configuration Of Operand Cache (Sh7751R)
Effective address 26 25 13 12 RAM area Longword (LW) determination selection [12:5] [13] Entry selection Address array Data array (way 0, way 1) (way 0, way 1) 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits...
Page 133: Read Operation
The U bit is never set to 1 while the cache is being used in write- through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, Memory-Mapped Cache Configuration (SH7751) and 4.6, Memory-Mapped Cache Configuration (SH7751R)). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Page 134: Write Operation
3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU.
Page 135 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data field of the cache line indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. A write is also performed to the corresponding external memory using the specified access size.
Page 136: Write-Back Buffer
Setting CCR.ORA to 1 enables 8 kbytes of the operand cache to be used as RAM. The operand cache entries used as RAM are the 8 kbytes of entries 128 to 255 and 384 to 511. In SH7751- compatible-mode in the SH7751R, the 8 kbytes of operand cache entries 256 to 511 are used as RAM.
Page 137 H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-kbyte RAM area. An example of RAM use in the SH7751R is shown below. SH7751-compatible-mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area (entries 256 to 511) A shadow of the RAM area occurs every 8 kbytes up to H'7FFF FFFF.
Page 138: Oc Index Mode
Prefetch Operation The SH7751 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance.
Page 139: Figure 4.6 Configuration Of Instruction Cache (Sh7751)
Figure 4.6 shows the configuration of the instruction cache in the SH7751. Figure 4.7 shows the configuration of the instruction cache in the SH7751R. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 [11:5] [12]...
Page 140: Figure 4.7 Configuration Of Instruction Cache (Sh7751R)
Effective address 13 12 11 10 Longword (LW) selection [11:5] [12] Entry selection Address array (way 0, way 1) Data array (way 0, way 1) 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit...
Page 141: Read Operation
LRU (SH7751R only) In a 2-way set-associative system, up to two entry addresses (among addresses 12 to 15) can register the same data in cache. The LRU bit indicates to which way the entry is to be registered among the two ways. There is one LRU bit in each entry, and it is controlled by hardware.
Page 142: Memory-Mapped Cache Configuration (Sh7751)
Memory-Mapped Cache Configuration (SH7751) To enable the IC and OC to be managed by software, the IC contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area.
Page 143: Ic Data Array
MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed.
Page 144: Oc Address Array
2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2 1 0 Address field 1 1 1 1 0 0 0 1...
Page 145: Oc Data Array
the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after write- back of that cache line, the tag, U bit, and V bit specified in the data field are written.
Page 146: Memory-Mapped Cache Configuration (Sh7751R)
Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified, and read values are undefined. Note that the memory-mapped cache configuration in SH7751-compatible-mode of the SH7751R is the same as that in the SH7751. Rev. 3.0, 04/02, page 107 of 1064...
Page 147: Ic Address Array
4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag and V bit are specified in the data field.
Page 148: Ic Data Array
5 4 3 2 1 0 Address field 1 1 1 1 0 0 0 0 Entry 10 9 Data field : Validity bit : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area.
Page 149: Oc Address Array
2 1 0 Address field 1 1 1 1 0 0 0 1 Entry Data field Longword data : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area.
Page 150: Oc Data Array
3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, each way’s tag stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set in bit [14] is ignored.
Page 151: Summary Of Memory-Mapped Oc Addresses
The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field.
Page 152: Store Queues
Store Queues Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory. When not using the SQs, the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.
Page 153 External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In the SH7751 Series, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register.
Page 154: Determination Of Sq Access Exception
If an exception occurs in an SQ write, the SQ contents may be corrupted in the SH7751 (see section 4.7.6, SQ Usage Notes), but the previous values of the SQ contents are guaranteed in the SH7751R. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted.
Page 155: Sq Usage Notes
If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7751, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs.
Page 156 Example 3: When an instruction at which an exception occurs is a branch instruction but a branch is not made Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ;...
Page 157 Rev. 3.0, 04/02, page 118 of 1064...
Page 158: Section 5 Exceptions
SH7751 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1.
Page 159: Register Descriptions
Register Descriptions There are three registers related to exception handling. Addresses are allocated for these, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.
Page 160: Exception Handling Functions
Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR) and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register 15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 161: Exception Types And Priorities
Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Reset Abort type Power-on reset H'A000 0000 —...
Page 162 Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340...
Page 163 Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral H-UDI H-UDI (VBR) H'600 H'600 type module GPIO GPIOI H'620 interrupt DMAC DMTE0 H'640 (module/ source) DMTE1 H'660 DMTE2 H'680 DMTE3 H'6A0...
Page 164: Exception Flow
Exception Flow 5.5.1 Exception Flow Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt).
Page 165: Exception Source Acceptance
5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline.
Page 166: Figure 5.3 Example Of General Exception Acceptance Order
Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Instruction fetch ID: Instruction decode EX: Instruction execution Instruction n+3 MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling:...
Page 167: Exception Requests And Bl Bit
5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU’s internal registers and the registers of the other modules are set to their post-reset state, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 168: Resets
5.6.1 Resets (1) Power-On Reset Sources: pin low level When the watchdog timer overflows while the WT/ bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. Transition address: H'A000 0000 Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a...
Page 169: Table 5.3 Types Of Reset
(2) Manual Reset Sources: pin low level and pin high level When a general exception other than a user break occurs while the BL bit is set to 1 in SR When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
Page 170 (3) H-UDI Reset Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) Transition address: H'A000 0000 Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111.
Page 171 (4) Instruction TLB Multiple-Hit Exception Source: Multiple ITLB address matches Transition address: H'A000 0000 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 172 (5) Data TLB Multiple-Hit Exception Source: Multiple UTLB address matches Transition address: H'A000 0000 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 173: General Exceptions
5.6.2 General Exceptions (1) Data TLB Miss Exception Source: Address mismatch in UTLB address comparison Transition address: VBR + H'0000 0400 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 174 (2) Instruction TLB Miss Exception Source: Address mismatch in ITLB address comparison Transition address: VBR + H'0000 0400 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 175 (3) Initial Page Write Exception Source: TLB is hit in a store access, but dirty bit D = 0 Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 176 (4) Data TLB Protection Violation Exception Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible Read/write access possible...
Page 177 (5) Instruction TLB Protection Violation Exception Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 178 (6) Data Address Error Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) Access to area H'8000 0000–H'FFFF FFFF in user mode Transition address: VBR + H'0000 0100...
Page 179 (7) Instruction Address Error Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 180 (8) Unconditional Trap Source: Execution of TRAPA instruction Transition address: VBR + H'0000 0100 Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 181 (9) General Illegal Instruction Exception Sources: Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR Transition address: VBR + H'0000 0100...
Page 182 (10) Slot Illegal Instruction Exception Sources: Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR Decoding in user mode of a privileged instruction in a delay slot...
Page 183 (11) General FPU Disable Exception Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 Transition address: VBR + H'0000 0100 Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 184 (12) Slot FPU Disable Exception Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 Transition address: VBR + H'0000 0100 Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 185 (13) User Breakpoint Trap Source: Fulfilling of a break condition set in the user break controller Transition address: VBR + H'0000 0100, or DBR Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 186 (14) FPU Exception Source: Exception due to execution of a floating-point operation Transition address: VBR + H'0000 0100 Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in EXPEVT.
Page 187: Interrupts
5.6.3 Interrupts (1) NMI Source: NMI pin edge detection Transition address: VBR + H'0000 0600 Transition operations: The PC and SR contents for the instruction at which this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 188 (2) IRL Interrupts Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). Transition address: VBR + H'0000 0600 Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC.
Page 189 (3) Peripheral Module Interrupts Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, PCIC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). Transition address: VBR + H'0000 0600 Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in...
Page 190: Priority Order With Multiple Exceptions
5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 191: Usage Notes
If the accepted exception (the highest-priority exception) is a delay slot instruction re- execution type exception, the branch instruction PR register write operation (PC operation performed in BSR, BSRF, JSR) is not inhibited. Usage Notes 1. Return from exception handling a.
Page 192: Restrictions
Restrictions 1. Restrictions on first instruction of exception handling routine Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register.
Page 193 Rev. 3.0, 04/02, page 154 of 1064...
Page 194: Section 6 Floating-Point Unit
A floating-point number consists of the following three fields: Sign (s) Exponent (e) Fraction (f) The SH7751 Series can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 23 22 Figure 6.1 Format of Single-Precision Floating-Point Number...
Page 195: Figure 6.2 Format Of Double-Precision Floating-Point Number
52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1. The two values E –...
Page 196: Non-Numbers (Nan)
Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000000 Positive normalized H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to number H'00100000 00000000 Positive denormalized...
Page 197: Denormalized Numbers
EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7751 Series as operation results are as follows: Single-precision qNaN: H'7FBFFFFF...
Page 198: Registers
Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;...
Page 199: Figure 6.4 Floating-Point Registers
FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14 FPR15_BANK0 FR15 XF15 FPR0_BANK1...
Page 200: Floating-Point Status/Control Register (Fpscr)
6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15;...
Page 201: Floating-Point Communication Register (Fpul)
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occurred, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 202: Floating-Point Exceptions
0, but the corresponding bit in the FPU exception flag field remains unchanged. Enable/disable exception handling The SH7751 Series supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases: FPU error (E): FPSCR.DN = 0 and a denormalized number is input Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)
Page 203: Graphics Support Functions
The number of significant digits is 24 for a normalized number and 23 for a denormalized number (number of leading zeros in the fractional part). In future version of SuperH series, the above error is guaranteed, but the same result as SH7751 Series is not guaranteed.
Page 204 This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 4 matrix, the SH7751 Series supports 4-dimensional operations. Matrix (4 matrix (4 This operation requires the execution of four FTRV instructions.
Page 205: Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, the SH7751 Series also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the SH7751 Series can perform data transfer by means of pair single- precision data transfer instructions. FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14;...
Page 206: Section 7 Instruction Set
Execution Environment PC: PC indicates the address of the instruction itself. Data sizes and data types: The SH7751 Series instruction set is implemented with 16-bit fixed- length instructions. The SH7751 Series can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access.
Page 207 In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution.
Page 208: Addressing Modes
Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 209 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + indirect with 4-bit displacement disp added. After disp is disp displacement zero-extended, it is multiplied by 1 (byte), 2 (word),...
Page 210 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 with disp added. After disp is zero-extended, it is + disp displacement multiplied by 2 (word), or 4 (longword), according...
Page 211: Table 7.1 Addressing Modes And Effective Addresses
Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp disp added after being sign-extended and Branch- multiplied by 2. Target PC + 4 + disp ×...
Page 212: Instruction Set
Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand Summary of Transfer direction operation (xx):...
Page 213: Table 7.3 Fixed-Point Transfer Instructions
Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit #imm,Rn sign extension 1110nnnniiiiiiii — — MOV.W @(disp,PC),Rn (disp 2 + PC + 4) sign 1001nnnndddddddd — — extension MOV.L @(disp,PC),Rn (disp 4 + PC & H'FFFFFFFC 1101nnnndddddddd — —...
Page 214 Table 7.3 Fixed-Point Transfer Instructions (cont) Instruction Operation Instruction Code Privileged T Bit MOV.B R0,@(disp,GBR) (disp + GBR) 11000000dddddddd — — MOV.W R0,@(disp,GBR) (disp 2 + GBR) 11000001dddddddd — — MOV.L R0,@(disp,GBR) (disp 4 + GBR) 11000010dddddddd — — MOV.B @(disp,GBR),R0 (disp + GBR) 11000100dddddddd —...
Page 215 Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rm,Rn Rn + Rm 0011nnnnmmmm1100 — — #imm,Rn Rn + imm 0111nnnniiiiiiii — — ADDC Rm,Rn Rn + Rm + T Rn, carry 0011nnnnmmmm1110 — Carry ADDV Rm,Rn Rn + Rm Rn, overflow 0011nnnnmmmm1111 —...
Page 216: Table 7.4 Arithmetic Operation Instructions
Table 7.4 Arithmetic Operation Instructions (cont) Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 — — word MAC.L @Rm+,@Rn+ Signed, (Rn) (Rm) + MAC...
Page 217: Table 7.5 Logic Operation Instructions
Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rm,Rn Rn & Rm 0010nnnnmmmm1001 — — #imm,R0 R0 & imm 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm (R0 + 11001101iiiiiiii — — GBR) Rm,Rn 0110nnnnmmmm0111 —...
Page 218: Table 7.6 Shift Instructions
Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit ROTL 0100nnnn00000100 — ROTR 0100nnnn00000101 — ROTCL 0100nnnn00100100 — ROTCR 0100nnnn00100101 — SHAD Rm,Rn When Rn 0, Rn << Rm 0100nnnnmmmm1100 — — When Rn < 0, Rn >> Rm [MSB SHAL 0100nnnn00100000 —...
Page 219: Table 7.7 Branch Instructions
Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit label When T = 0, disp 2 + PC + 10001011dddddddd — — When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd — — disp 2 + PC + 4 When T = 1, nop...
Page 220: Table 7.8 System Control Instructions
Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit CLRMAC MACH, MACL 0000000000101000 — — CLRS 0000000001001000 — — CLRT 0000000000001000 — Rm,SR 0100mmmm00001110 Privileged Rm,GBR 0100mmmm00011110 — — Rm,VBR 0100mmmm00101110 Privileged — Rm,SSR 0100mmmm00111110 Privileged — Rm,SPC 0100mmmm01001110 Privileged —...
Page 221 Table 7.8 System Control Instructions (cont) Instruction Operation Instruction Code Privileged T Bit SETS 0000000001011000 — — SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR,Rn 0000nnnn00000010 Privileged — GBR,Rn 0000nnnn00010010 — — VBR,Rn 0000nnnn00100010 Privileged — SSR,Rn 0000nnnn00110010 Privileged —...
Page 222: Table 7.9 Floating-Point Single-Precision Instructions
Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FLDI0 H'00000000 1111nnnn10001101 — — FLDI1 H'3F800000 1111nnnn10011101 — — FMOV FRm,FRn 1111nnnnmmmm1100 — — FMOV.S @Rm,FRn (Rm) 1111nnnnmmmm1000 — — FMOV.S @(R0,Rm),FRn (R0 + Rm) 1111nnnnmmmm0110 — —...
Page 223: Table 7.10 Floating-Point Double-Precision Instructions
Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — FFFF FADD DRm,DRn DRn + DRm 1111nnn0mmm00000 — — FCMP/EQ DRm,DRn When DRn = DRm, 1 1111nnn0mmm00100 — Comparison Otherwise, 0 result FCMP/GT...
Page 224: Table 7.12 Floating-Point Graphics Acceleration Instructions
Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit FMOV DRm,XDn 1111nnn1mmm01100 — — FMOV XDm,DRn 1111nnn0mmm11100 — — FMOV XDm,XDn 1111nnn1mmm11100 — — FMOV @Rm,XDn (Rm) 1111nnn1mmmm1000 — — FMOV @Rm+,XDn (Rm) XDn, Rm + 8 1111nnn1mmmm1001 —...
Page 225 Rev. 3.0, 04/02, page 186 of 1064...
Page 226: Section 8 Pipelining
Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7751 Series. Pipelines Figure 8.1 shows the basic pipelines.
Page 227: Figure 8.1 Basic Pipelines
1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction • Address •...
Page 228: Figure 8.2 Instruction Execution Patterns
1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.
Page 229 10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.
Page 230 19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.
Page 231 31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.
Page 232 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle : Cannot overlap a stage of the same kind, except when two instructions are Notes: executed in parallel.
Page 233: Parallel-Executability
Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.
Page 234 Table 8.1 Instruction Groups (cont) 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W...
Page 235 Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV...
Page 236 Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L...
Page 237: Execution Cycles And Pipeline Stalling
Table 8.2 Parallel-Executability 2nd Instruction Instruction O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: I-clock: CPU, FPU, MMU, caches B-clock: External bus controller P-clock: Peripheral units...
Page 238 The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 239 Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that attempts to use the locked resource is stalled (figure 8.3 (h)).
Page 240: Figure 8.3 Examples Of Pipelined Execution
(a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction. (b)