Hitachi SH7751 Hardware Manual

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Regarding the change of names mentioned in the document, such as

Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were

transferred to Renesas Technology Corporation on April 1st 2003.

These operations include microcomputer, logic, analog and discrete devices,

and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,

and other Hitachi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp.

Thank you for your understanding. Except for our corporate trademark,

logo and corporate statement, no changes whatsoever have been made to the

contents of the document, and these changes do not constitute any alteration

to the contents of the document itself.

Renesas Technology Corp.

Renesas Technology Home Page: www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

Table of Contents

6
Table of Contents
40
Section 1 Overview
40
SH7751 Series Features
41
Figure 13.61 MPX Interface Timing
41
Table 1.1 SH7751 Series Features
49
Block Diagram
49
Figure 1.1 Block Diagram of SH7751 Series Functions
50
Pin Arrangement
50
Figure 1.2 Pin Arrangement (256-Pin QFP)
51
Figure 1.3 Pin Arrangement (256-Pin BGA)
52
Pin Functions
- 52
  Pin Functions (256-Pin QFP)
- 52
  Table 1.2 Pin Functions
- 63
  Pin Functions (256-Pin BGA)
- 63
  Table 1.3 Pin Functions
74
Section 2 Programming Model
74
Data Formats
74
Figure 2.1 Data Formats
75
Register Configuration
- 75
  Privileged Mode and Banks
- 76
  Table 2.1 Initial Register Values
- 77
  Figure 2.2 CPU Register Configuration in Each Processor Mode
- 78
  General Registers
- 79
  Figure 2.3 General Registers
- 80
  Floating-Point Registers
- 81
  Figure 2.4 Floating-Point Registers
- 82
  Control Registers
- 83
  System Registers
85
Memory-Mapped Registers
86
Data Format in Registers
86
Data Formats in Memory
86
Figure 2.5 Data Formats in Memory
87
Processor States
88
Processor Modes
88
Figure 2.6 Processor State Transitions
90
Memory Management Unit (MMU)
90
Overview
- 90
  Features
- 90
  Role of the MMU
- 92
  Figure 3.1 Role of the MMU
- 93
  Register Configuration
- 93
  Caution
- 93
  Table 3.1 MMU Registers
94
Register Descriptions
94
Figure 3.2 Mmu-Related Registers
97
Address Space
- 97
  Physical Address Space
- 98
  Figure 3.3 Physical Address Space (MMUCR.AT = 0)
- 99
  Figure 3.4 P4 Area
- 100
  External Memory Space
- 100
  Figure 3.5 External Memory Space
- 101
  Virtual Address Space
- 101
  Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
- 102
  On-Chip RAM Space
- 102
  Address Translation
- 103
  Single Virtual Memory Mode and Multiple Virtual Memory Mode
- 103
  Address Space Identifier (ASID)
104
TLB Functions
- 104
  Unified TLB (UTLB) Configuration
- 104
  Figure 3.7 UTLB Configuration
- 105
  Figure 3.8 Relationship Between Page Size and Address Format
- 108
  Instruction TLB (ITLB) Configuration
- 108
  Address Translation Method
- 108
  Figure 3.9 ITLB Configuration
- 109
  Figure 3.10 Flowchart of Memory Access Using UTLB
- 110
  Figure 3.11 Flowchart of Memory Access Using ITLB
111
MMU Functions
- 111
  MMU Hardware Management
- 111
  MMU Software Management
- 111
  MMU Instruction (LDTLB)
- 112
  Hardware ITLB Miss Handling
- 112
  Figure 3.12 Operation of LDTLB Instruction
- 113
  Avoiding Synonym Problems
114
MMU Exceptions
- 114
  Instruction TLB Multiple Hit Exception
- 114
  Instruction TLB Miss Exception
- 115
  Instruction TLB Protection Violation Exception
- 116
  Data TLB Multiple Hit Exception
- 117
  Data TLB Miss Exception
- 118
  Data TLB Protection Violation Exception
- 118
  Initial Page Write Exception
119
Memory-Mapped TLB Configuration
- 120
  ITLB Address Array
- 120
  Figure 3.13 Memory-Mapped ITLB Address Array
- 121
  ITLB Data Array 1
- 121
  Figure 3.14 Memory-Mapped ITLB Data Array 1
- 122
  ITLB Data Array 2
- 122
  UTLB Address Array
- 122
  Figure 3.15 Memory-Mapped ITLB Data Array 2
- 123
  Figure 3.16 Memory-Mapped UTLB Address Array
- 124
  UTLB Data Array 1
- 124
  Figure 3.17 Memory-Mapped UTLB Data Array 1
- 125
  UTLB Data Array 2
- 125
  Figure 3.18 Memory-Mapped UTLB Data Array 2
126
Section 4 Caches
126
Overview
- 126
  Features
- 126
  Table 4.1 Cache Features (SH7751)
- 127
  Register Configuration
- 127
  Table 4.2 Cache Features (SH7751R)
- 127
  Table 4.3 Store Queue Features
- 127
  Table 4.4 Cache Control Registers
128
Register Descriptions
128
Figure 4.1 Cache and Store Queue Control Registers (CCR)
130
Operand Cache (OC)
- 130
  Configuration
- 131
  Figure 4.2 Configuration of Operand Cache (SH7751)
- 132
  Figure 4.3 Configuration of Operand Cache (SH7751R)
- 133
  Read Operation
- 134
  Write Operation
- 136
  Write-Back Buffer
- 136
  Write-Through Buffer
- 136
  RAM Mode
- 136
  Figure 4.4 Configuration of Write-Back Buffer
- 136
  Figure 4.5 Configuration of Write-Through Buffer
- 138
  OC Index Mode
- 138
  Coherency Between Cache and External Memory
- 138
  Prefetch Operation
138
Instruction Cache (IC)
- 138
  Configuration
- 139
  Figure 4.6 Configuration of Instruction Cache (SH7751)
- 140
  Figure 4.7 Configuration of Instruction Cache (SH7751R)
- 141
  Read Operation
- 141
  IC Index Mode
142
Memory-Mapped Cache Configuration (SH7751)
- 142
  IC Address Array
- 143
  IC Data Array
- 143
  Figure 4.8 Memory-Mapped IC Address Array
- 144
  OC Address Array
- 144
  Figure 4.9 Memory-Mapped IC Data Array
- 145
  OC Data Array
- 145
  Figure 4.10 Memory-Mapped OC Address Array
146
Memory-Mapped Cache Configuration (SH7751R)
- 146
  Figure 4.11 Memory-Mapped OC Data Array
- 147
  IC Address Array
- 148
  Figure 4.12 Memory-Mapped IC Address Array
- 148
  IC Data Array
- 149
  Figure 4.13 Memory-Mapped IC Data Array
- 149
  OC Address Array
- 150
  Figure 4.14 Memory-Mapped OC Address Array
- 150
  OC Data Array
- 151
  Figure 4.15 Memory-Mapped OC Data Array
- 151
  Summary of Memory-Mapped OC Addresses
152
Store Queues
- 152
  SQ Configuration
- 152
  SQ Writes
- 152
  Transfer to External Memory
- 152
  Figure 4.16 Store Queue Configuration
- 154
  Determination of SQ Access Exception
- 154
  SQ Read (SH7751R Only)
- 155
  SQ Usage Notes
158
Section 5 Exceptions
158
Overview
- 158
  Features
- 158
  Register Configuration
- 158
  Table 5.1 Exception-Related Registers
159
Register Descriptions
159
Figure 5.1 Register Bit Configurations
160
Exception Handling Functions
- 160
  Exception Handling Flow
- 160
  Exception Handling Vector Addresses
161
Exception Types and Priorities
161
Table 5.2 Exceptions
164
Exception Flow
- 164
  Figure 5.2 Instruction Execution and Exception Handling
- 165
  Exception Source Acceptance
- 166
  Figure 5.3 Example of General Exception Acceptance Order
- 167
  Exception Requests and BL Bit
- 167
  Return From Exception Handling
167
Description of Exceptions
- 168
  Resets
- 169
  Table 5.3 Types of Reset
- 173
  General Exceptions
- 187
  Interrupts
- 190
  Priority Order with Multiple Exceptions
191
Usage Notes
192
Restrictions
194
Section 6 Floating-Point Unit
194
Overview
194
Data Formats
- 194
  Floating-Point Format
- 194
  Figure 6.1 Format of Single-Precision Floating-Point Number
- 195
  Figure 6.2 Format of Double-Precision Floating-Point Number
- 195
  Table 6.1 Floating-Point Number Formats and Parameters
- 196
  Non-Numbers (Nan)
- 196
  Table 6.2 Floating-Point Ranges
- 197
  Denormalized Numbers
- 197
  Figure 6.3 Single-Precision Nan Bit Pattern
198
Registers
- 198
  Floating-Point Registers
- 199
  Figure 6.4 Floating-Point Registers
- 200
  Floating-Point Status/Control Register (FPSCR)
- 201
  Floating-Point Communication Register (FPUL)
201
Rounding
202
Floating-Point Exceptions
203
Graphics Support Functions
- 203
  Geometric Operation Instructions
- 205
  Pair Single-Precision Data Transfer
206
Section 7 Instruction Set
206
Execution Environment
208
Addressing Modes
211
Table 7.1 Addressing Modes and Effective Addresses
212
Instruction Set
212
Table 7.2 Notation Used in Instruction List
213
Table 7.3 Fixed-Point Transfer Instructions
216
Table 7.4 Arithmetic Operation Instructions
217
Table 7.5 Logic Operation Instructions
218
Table 7.6 Shift Instructions
219
Table 7.7 Branch Instructions
220
Table 7.8 System Control Instructions
222
Table 7.9 Floating-Point Single-Precision Instructions
223
Table 7.10 Floating-Point Double-Precision Instructions
223
Table 7.11 Floating-Point Control Instructions
224
Table 7.12 Floating-Point Graphics Acceleration Instructions
226
Section 8 Pipelining
226
Pipelines
227
Figure 8.1 Basic Pipelines
228
Figure 8.2 Instruction Execution Patterns
233
Parallel-Executability
233
Table 8.1 Instruction Groups
237
Execution Cycles and Pipeline Stalling
237
Table 8.2 Parallel-Executability
240
Figure 8.3 Examples of Pipelined Execution
244
Table 8.3 Execution Cycles
254
Section 9 Power-Down Modes
254
Overview
- 254
  Types of Power-Down Modes
- 255
  Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
- 256
  Register Configuration
- 256
  Pin Configuration
- 256
  Table 9.2 Power-Down Mode Registers
- 256
  Table 9.3 Power-Down Mode Pins
257
Register Descriptions
- 257
  Standby Control Register (STBCR)
- 259
  Peripheral Module Pin High Impedance Control
- 259
  Peripheral Module Pin Pull-Up Control
- 260
  Standby Control Register 2 (STBCR2)
- 261
  Clock Stop Register 00 (CLKSTP00)
- 262
  Clock Stop Clear Register 00 (CLKSTPCLR00)
263
Sleep Mode
- 263
  Transition to Sleep Mode
- 263
  Exit From Sleep Mode
263
Deep Sleep Mode
- 263
  Transition to Deep Sleep Mode
- 264
  Exit From Deep Sleep Mode
264
Pin Sleep Mode
- 264
  Transition to Pin Sleep Mode
- 264
  Exit From Pin Sleep Mode
264
Standby Mode
- 264
  Transition to Standby Mode
- 265
  Exit From Standby Mode
- 265
  Table 9.4 State of Registers in Standby Mode
- 266
  Clock Pause Function
266
Module Standby Function
- 266
  Transition to Module Standby Function
- 267
  Exit From Module Standby Function
268
Hardware Standby Mode
- 268
  Transition to Hardware Standby Mode
- 268
  Exit From Hardware Standby Mode
- 269
  Usage Notes
269
STATUS Pin Change Timing
- 269
  In Reset
- 269
  Figure 9.1 STATUS Output in Power-On Reset
- 270
  In Exit From Standby Mode
- 270
  Figure 9.2 STATUS Output in Manual Reset
- 270
  Figure 9.3 STATUS Output in Standby Interrupt Sequence
- 271
  Figure 9.4 STATUS Output in Standby Power-On Reset Sequence
- 272
  In Exit From Sleep Mode
- 272
  Figure 9.5 STATUS Output in Standby Manual Reset Sequence
- 272
  Figure 9.6 STATUS Output in Sleep Interrupt Sequence
- 273
  Figure 9.7 STATUS Output in Sleep Power-On Reset Sequence
- 274
  Figure 9.8 STATUS Output in Sleep Manual Reset Sequence
- 275
  In Exit From Deep Sleep Mode
- 275
  Figure 9.9 STATUS Output in Deep Sleep Interrupt Sequence
- 275
  Figure 9.10 STATUS Output in Deep Sleep Power-On Reset Sequence
- 276
  Figure 9.11 STATUS Output in Deep Sleep Manual Reset Sequence
- 277
  Hardware Standby Mode Timing
- 277
  Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
- 278
  Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
- 278
  Figure 9.14 Timing When Power Other Than VDD-RTC Is Off
- 279
  Figure 9.15 Timing When VDD-RTC Power Is Off On
280
Section 10 Clock Oscillation Circuits
280
Overview
- 280
  Features
282
Overview of CPG
- 282
  Block Diagram of CPG
- 282
  Figure 10.1(1) Block Diagram of CPG (SH7751)
- 283
  Figure 10.1(2) Block Diagram of CPG (SH7751R)
- 285
  CPG Pin Configuration
- 285
  CPG Register Configuration
- 285
  Table 10.1 CPG Pins
- 285
  Table 10.2 CPG Register
286
Clock Operating Modes
286
Table 10.3(1) Clock Operating Modes (SH7751)
286
Table 10.3(2) Clock Operating Modes (SH7751R)
287
Table 10.4 FRQCR Settings and Internal Clock Frequencies
288
CPG Register Description
- 288
  Frequency Control Register (FRQCR)
290
Changing the Frequency
- 290
  Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
- 290
  Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
- 291
  Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
- 291
  Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
- 291
  Changing CPU or Peripheral Module Clock Division Ratio

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Summary of Contents for Hitachi SH7751

Page 1 DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark,...
Page 2 Hitachi SuperH RISC engine SH7751 Series SH7751, SH7751R Hardware Manual ADE-602-201B Rev. 3.0 4/11/2002 Hitachi, Ltd.
Page 3 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7751 Series is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and PCI controller (PCIC).
Page 5 User manuals for SH7751 and SH7751R Name of Document Document No. SH7751 Series Hardware Manual This manual SH-4 Programming Manual ADE-602-156 User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual...
Page 6: Table Of Contents
Contents Section 1 Overview ......................SH7751 Series Features..................... Block Diagram ........................10 Pin Arrangement ....................... 11 Pin Functions........................13 1.4.1 Pin Functions (256-Pin QFP) ................13 1.4.2 Pin Functions (256-Pin BGA) ................24 Section 2 Programming Model ..................35 Data Formats ........................35 Register Configuration ......................
Page 7 3.4.2 Instruction TLB (ITLB) Configuration ..............69 3.4.3 Address Translation Method ................69 MMU Functions ........................ 72 3.5.1 MMU Hardware Management ................72 3.5.2 MMU Software Management................72 3.5.3 MMU Instruction (LDTLB) ................. 72 3.5.4 Hardware ITLB Miss Handling................73 3.5.5 Avoiding Synonym Problems ................
Page 8 Memory-Mapped Cache Configuration (SH7751) ............103 4.5.1 IC Address Array ....................103 4.5.2 IC Data Array ....................... 104 4.5.3 OC Address Array ....................105 4.5.4 OC Data Array ..................... 106 Memory-Mapped Cache Configuration (SH7751R) ............107 4.6.1 IC Address Array ....................108 4.6.2...
Page 9 Data Formats ........................155 6.2.1 Floating-Point Format ..................155 6.2.2 Non-Numbers (NaN).................... 157 6.2.3 Denormalized Numbers..................158 Registers ..........................159 6.3.1 Floating-Point Registers ..................159 6.3.2 Floating-Point Status/Control Register (FPSCR) ..........161 6.3.3 Floating-Point Communication Register (FPUL)..........162 Rounding ........................... 162 Floating-Point Exceptions ....................
Page 10 9.5.1 Transition to Pin Sleep Mode................225 9.5.2 Exit from Pin Sleep Mode ..................225 Standby Mode ........................225 9.6.1 Transition to Standby Mode ................. 225 9.6.2 Exit from Standby Mode ..................226 9.6.3 Clock Pause Function................... 227 Module Standby Function ....................227 9.7.1 Transition to Module Standby Function...............
Page 11 10.8.3 Notes on Register Access ..................257 10.9 Using the WDT ......................... 258 10.9.1 Standby Clearing Procedure................. 258 10.9.2 Frequency Changing Procedure ................258 10.9.3 Using Watchdog Timer Mode................259 10.9.4 Using Interval Timer Mode.................. 259 10.10 Notes on Board Design...................... 260 Section 11 Realtime Clock (RTC) ..................
Page 12 Section 12 Timer Unit (TMU) ..................287 12.1 Overview ........................... 287 12.1.1 Features ........................ 287 12.1.2 Block Diagram ..................... 288 12.1.3 Pin Configuration ....................288 12.1.4 Register Configuration ..................289 12.2 Register Descriptions......................290 12.2.1 Timer Output Control Register (TOCR) .............. 290 12.2.2 Timer Start Register (TSTR) ................
Page 13 .......... 463 14.1 Overview ........................... 463 14.1.1 Features ........................ 463 14.1.2 Block Diagram (SH7751)..................466 14.1.3 Pin Configuration (SH7751) ................467 14.1.4 Register Configuration (SH7751) ................ 468 14.2 Register Descriptions......................470 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........... 470 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) ........471 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......
Page 14 14.4.1 Examples of Transfer between External Memory and an External Device with DACK ......................519 14.5 On-Demand Data Transfer Mode (DDT Mode) ..............520 14.5.1 Operation......................520 14.5.2 Pins in DDT Mode ....................522 14.5.3 Transfer Request Acceptance on Each Channel........... 525 14.5.4 Notes on Use of DDT Module ................
Page 15 15.3.2 Operation in Asynchronous Mode................ 599 15.3.3 Multiprocessor Communication Function ............609 15.3.4 Operation in Synchronous Mode................618 15.4 SCI Interrupt Sources and DMAC..................627 15.5 Usage Notes........................628 Section 16 Serial Communication Interface with FIFO (SCIF) ......633 16.1 Overview ........................... 633 16.1.1 Features ........................
Page 16 17.3.1 Overview ......................686 17.3.2 Pin Connections....................687 17.3.3 Data Format......................688 17.3.4 Register Settings....................689 17.3.5 Clock ........................691 17.3.6 Data Transfer Operations ..................694 17.4 Usage Notes........................701 Section 18 I/O Ports ......................707 18.1 Overview ........................... 707 18.1.1 Features ........................
Page 17 20.6.1 Transition to User Break Controller Stopped State ..........775 20.6.2 Cancelling the User Break Controller Stopped State ........... 775 20.6.3 Examples of Stopping and Restarting the User Break Controller ......776 Section 21 Hitachi User Debug Interface (H-UDI) ............ 777 21.1 Overview ........................... 777 21.1.1 Features ........................
Page 18 21.1.3 Pin Configuration ....................779 21.1.4 Register Configuration ..................780 21.2 Register Descriptions......................781 21.2.1 Instruction Register (SDIR).................. 781 21.2.2 Data Register (SDDR)..................782 21.2.3 Bypass Register (SDBPR)..................782 21.2.4 Interrupt Factor Register (SDINT) ............... 783 21.2.5 Boundary Scan Register (SDBSR) ............... 783 21.3 Operation...........................
Page 19 22.2.21 PCI Interrupt Mask Register (PCIINTM)............. 848 22.2.22 PCI Address Data Register at Error (PCIALR)............ 850 22.2.23 PCI Command Data Register at Error (PCICLR)..........851 22.2.24 PCI Arbiter Interrupt Register (PCIAINT)............853 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM) ..........855 22.2.26 PCI Error Bus Master Data Register (PCIBMLR) ..........
Page 20 22.6.2 Interrupts from External PCI Devices ..............921 22.6.3 ........................921 22.7 Error Detection ........................922 22.8 PCIC Clock ........................922 22.9 Power Management......................923 22.9.1 Power Management Overview ................923 22.9.2 Stopping the Clock ....................924 22.9.3 Compatibility with Standby and Sleep ..............927 22.10 Port Functions ........................
Page 21 Figures Figure 1.1 Block Diagram of SH7751 Series Functions ........... Figure 1.2 Pin Arrangement (256-Pin QFP)..............Figure 1.3 Pin Arrangement (256-Pin BGA) ..............Figure 2.1 Data Formats....................Figure 2.2 CPU Register Configuration in Each Processor Mode ........Figure 2.3 General Registers .....................
Page 22 Timing When Power Other than VDD-RTC is Off ......... 239 Figure 9.15 Timing When VDD-RTC Power is Off On ..........240 Figure 10.1(1) Block Diagram of CPG (SH7751) ..............243 Figure 10.1(2) Block Diagram of CPG (SH7751R)..............244 Figure 10.2 Block Diagram of WDT................... 253 Figure 10.3...
Page 23 Figure 12.7 Operation Timing when Using Input Capture Function........302 Figure 13.1 Block Diagram of BSC ..................307 Figure 13.2 Correspondence between Virtual Address Space and External Memory Space 311 Figure 13.3 External Memory Space Allocation ..............313 Figure 13.4 Example of Sampling Timing at which BCR4 is Set (Two Wait Cycles are Inserted by WCR2) ............
Page 24 Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle ..................... 410 Figure 13.35 Auto-Refresh Operation................... 411 Figure 13.36 Synchronous DRAM Auto-Refresh Timing ............ 412 Figure 13.37 Synchronous DRAM Self-Refresh Timing ............413 Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL) ......... 415 Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ....
Page 25 Figure 13.62 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................445 Figure 13.63 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................
Page 26 Figure 14.15 Dual Address Mode/Burst Mode External Bus External Bus/ (Edge Detection), DACK (Read Cycle) ..........508 Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) External Bus..................... 509 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus On-Chip SCI (Level Detection) .....................
Page 27 Figure 14.40 Write to Synchronous DRAM (Row Hit) ............536 Figure 14.41 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ........537 Figure 14.42 DDT Mode Setting................... 538 Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device External Bus Data Transfer................
Page 28 Figure 15.10 Sample Serial Reception Flowchart (1) ............606 Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ....................609 Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)........610 Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart........
Page 29 Figure 17.7 Sample Initialization Flowchart ............... 695 Figure 17.8 Sample Transmission Processing Flowchart............ 697 Figure 17.9 Sample Reception Processing Flowchart ............699 Figure 17.10 Receive Data Sampling Timing in Smart Card Mode........701 Figure 17.11 Retransfer Operation in SCI Receive Mode............. 702 Figure 17.12 Retransfer Operation in SCI Transmit Mode ...........
Page 30 Figure 22.19 Endian Control for Local Bus ................912 Figure 22.20 Data Alignment at DMA Transfer ..............913 Figure 22.21(1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) .... 915 Figure 22.21(2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus)..916 Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) .
Page 31 Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) ...... 981 Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)......982 Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD [1:0] = 01, TRWL [2:0] = 010)............
Page 32 Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001, TRC [2:0] = 001) ............. 1004 Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001)......1005 Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait........................
Page 33 Figure 23.67 H-UDI Data Transfer Timing ................1021 Figure 23.68 Pin Break Timing..................... 1021 Figure 23.69 NMI Input Timing ................... 1022 Figure 23.70 PCI Clock Input Timing................... 1025 Figure 23.71 Output Signal Timing ..................1025 Figure 23.72 Output Signal Timing ..................1026 Figure 23.73 I/O Port Input/Output Timing ................
Page 34 State of Registers in Standby Mode ..............226 Table 10.1 CPG Pins ......................246 Table 10.2 CPG Register...................... 246 Table 10.3(1) Clock Operating Modes (SH7751)..............247 Table 10.3(2) Clock Operating Modes (SH7751R) ..............247 Table 10.4 FRQCR Settings and Internal Clock Frequencies ..........248 Table 10.5 WDT Registers....................
Page 35 Table 13.14 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing 379 Table 13.15 Example of Correspondence between SH7751 Series and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0) ..395 Table 13.16 Cycles in Which Pipelined Access Can Be Used ..........409 Table 13.17...
Page 36 Table 15.2 SCI Registers...................... 572 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ..... 591 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode....594 Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)..................
Page 37 Table 21.3 Structure of Boundary Scan Register ..............784 Table 22.1 Pin Configuration ....................804 Table 22.2 List of PCI Configuration Registers ..............806 Table 22.3 PCI Configuration Register Configuration............807 Table 22.4 List of PCIC Local Registers................808 Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)......
Page 38 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) ................... 1027 Table A.1 Address List......................1031 Table C.1 Clock Operating Modes (SH7751)..............1041 Table C.2 Clock Operating Modes (SH7751R) ..............1041 Table C.3 Area 0 Memory Map and Bus Width ..............1042 Table C.4...
Page 39 Rev. 3.0, 04/02, page xxxviii of xxxviii...
Page 40: Section 1 Overview
50% reduction in program size over a 32-bit instruction set. The SH7751 Series feature the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751 Series have an instruction cache, an...
Page 41: Figure 13.61 Mpx Interface Timing
Table 1.1 SH7751 Series Features Item Features Operating frequency: 240 MHz* /200 MHz* /167 MHz* /133 MHz* Performance: 430 MIPS (240 MHz), 360 MIPS (200 MHz) 300 MIPS (167 MHz), 240 MIPS (133 MHz) 1.2 GFLOPS (167 MHz), 0.93 GFLOPS (133 MHz) 1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz)
Page 42 Table 1.1 SH7751 Series Features (cont) Item Features Original Hitachi SuperH architecture 32-bit internal data bus General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers RISC-type instruction set (upward-compatible with SuperH Series)
Page 43 Table 1.1 SH7751 Series Features (cont) Item Features On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt...
Page 44 Clock pulse Choice of main clock generator (CPG) SH7751: 1/2, 1, 3, or 6 times EXTAL SH7751R: 1, 6, or 12 times EXTAL Clock modes: (Maximum frequency: Varies with models) CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock...
Page 45 [SH7751R] 16 kbytes, 2-way set associative 256 entries/way, 32-byte block length Cache-double-mode (16-kbyte cache) Index mode SH7751-compatible mode (8 kbytes, direct mapping) Operand cache (OC) 32 kbytes, 2-way set associative 512 entries/way, 32-byte block length Cache-double-mode (32-kbyte cache) Index mode...
Page 46 Table 1.1 SH7751 Series Features (cont) Item Features Interrupt controller Five independent external interrupts (NMI, IRL3 to IRL0) (INTC) 15-level signed external interrupts: IRL3 to IRL0 On-chip peripheral module interrupts: Priority level can be set for each module User break...
Page 47 Table 1.1 SH7751 Series Features (cont) Item Features Direct memory Physical address DMA controller access controller SH7751: 4-channel (DMAC) SH7751R: 8-channel Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes Address modes: 1-bus-cycle single address mode 2-bus-cycle dual address mode...
Page 48 Table 1.1 SH7751 Series Features (cont) Item Features PCI bus controller PCI bus controller (Rev.2.1-compatible)* (PCIC) 32-bit bus 33 MHz/66 MHz support PCI master/slave support PCI host function support Built-in bus arbiter 4 built-in PCI-dedicated DMAC (direct memory access controller)
Page 49: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram of the SH7751 Series. Lower 32-bit data Cache and I cache ITLB UTLB O cache controller INTC DMAC (SCIF) PCIC (PCI)DMAC BSC: Bus state controller CPG: Clock pulse generator DMAC: Direct memory access controller...
Page 50: Pin Arrangement
Pin Arrangement XTAL2 EXTAL2 VDD-RTC VSS-RTC PCICLK IDSEL /MD9 /MD10 MD6/ MD2/RXD2 QFP256 TCLK MD8/ MD1/TXD2 MD0/SCK2 MD7/ (Top view) AUDSYNC AUDCK AUDATA0 AUDATA1 AUDATA2 AUDATA3 Reserved MD3/ MD4/ VDD (internal) DACK0 VSS (internal) DACK1 DRAK0 DRAK1 VDDQ (IO) STATUS0 VSSQ (IO) STATUS1 /BRKACK...
Page 51: Figure 1.3 Pin Arrangement (256-Pin Bga)
BGA256 (Top view) VDDQ(IO) VSS (internal) VDD-CPG/RTC VSSQ(IO) VSS-CPG/RTC VDD-PLL1/2 VDD (internal) VSS-PLL1/2 Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * May be connected to V Figure 1.3 Pin Arrangement (256-Pin BGA) Rev.
Page 52: Pin Functions
Pin Functions 1.4.1 Pin Functions (256-Pin QFP) Table 1.2 Pin Functions Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND Data in (H-UDI) Chip select 0 Chip select 1 Chip select 4 ...
Page 53 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data D7–D0 DQM0 DQM0 select signal D15–D8...
Page 54 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND Address Address Address Address...
Page 55 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD Power Internal GND Address 100 A19 Address...
Page 56 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus grant (host function) Bus request (host function) Bus request MD10 MD10 (host function)/ mode 119 VDDQ Power IO VDD 120 VSSQ Power IO GND ...
Page 57 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 134 AD28 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 135 AD27 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 136 AD26 PCI address/ (Port) (Port) (Port)
Page 58 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Device select 157 VDDQ Power IO VDD 158 VSSQ Power IO GND Transaction stop Exclusive access Parity error 162 PAR Parity 163 C/ Command/...
Page 59 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 179 AD5 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 180 AD4 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 181 AD3 PCI address/ (Port) (Port) (Port)
Page 60 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX acknowledge/ bus request request/bus acknowledge 204 MD6/ Mode/ (PCMCIA) Bus ready 206 TXD SCI data output 207 VDDQ Power IO VDD 208 VSSQ...
Page 61 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 225 VDD Power Internal VDD 226 VSS Power Internal GND 227 AUDATA2 AUD data 228 AUDATA3 AUD data 229 Reserved Do not connect 230 MD3/...
Page 62 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 247 VDDQ Power IO VDD 248 VSSQ Power IO GND 249 VDD-PLL2 Power PLL2 VDD 250 VSS-PLL2 Power PLL2 GND 251 VDD-PLL1 Power PLL1 VDD 252 VSS-PLL1 Power PLL1 GND 253 VDD-CPG...
Page 63: Pin Functions (256-Pin Bga)
1.4.2 Pin Functions (256-Pin BGA) Table 1.3 Pin Functions Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND Data in (H-UDI) Chip select 0 Chip select 1 Chip select 4 Chip select 5...
Page 64 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data D7–D0 DQM0 DQM0 select signal D15–D8 DQM1 DQM1 select signal...
Page 65 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND Address Address Address Address ...
Page 66 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD Power Internal GND Address Address Address...
Page 67 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Bus grant (host function) Bus request (host function) Bus request MD10 MD10 (host function)/ mode VDDQ Power IO VDD VSSQ Power IO GND Bus request...
Page 68 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AD26 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD25 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD24 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port...
Page 69 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Transaction stop Exclusive access Parity error Parity Command/ byte enable AD15 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD14...
Page 70 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port VDDQ Power I/O VDD...
Page 71 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA request/bus acknowledge MD6/ Mode/ (PCMCIA) Bus ready SCI data output VDDQ Power IO VDD VSSQ Power IO GND Power Internal VDD Power Internal GND...
Page 72 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AUDATA2 AUD data AUDATA3 AUD data Do not connect MD3/ Mode/ PCMCIA-CE MD4/ Mode/ PCMCIA-CE Mode VDDQ Power IO VDD VSSQ Power IO GND...
Page 73 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSS-PLL2 Power PLL2 GND VDD-PLL1 Power PLL1 VDD VSS-PLL1 Power PLL1 GND VDD-CPG Power CPG VDD VSS-CPG Power CPG GND XTAL Crystal resonator EXTAL External input clock/crystal resonator...
Page 74: Section 2 Programming Model
Section 2 Programming Model Data Formats The data formats handled by the SH7751 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 75: Register Configuration
Processor Modes: The SH7751 Series has two processor modes, user mode and privileged mode. The SH7751 Series normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be...
Page 76: Table 2.1 Initial Register Values
Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.
Page 77: Figure 2.2 Cpu Register Configuration In Each Processor Mode
R0 _ BANK0* R0 _ BANK1* R0 _ BANK0* R1 _ BANK0* R1 _ BANK0* R1 _ BANK1* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK1* R3 _ BANK0* R4 _ BANK0* R4 _ BANK0* R4 _ BANK1* R5 _ BANK0* R5 _ BANK1*...
Page 78: General Registers
R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7751 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
Page 79: Figure 2.3 General Registers
SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...
Page 80: Floating-Point Registers
2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Page 81: Figure 2.4 Floating-Point Registers
Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0...
Page 82: Control Registers
Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X = undefined)) 31 30 29 28 27 16 15 14 —...
Page 83: System Registers
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 84 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15;...
Page 85: Memory-Mapped Registers
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 86: Data Format In Registers
Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Longword Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.
Page 87: Processor States
Note: The SH7751 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. Processor States The SH7751 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state.
Page 88: Processor Modes
From any state when From any state when RESET = 0 RESET = 1 and MRESET = 0 Power-on reset state Manual reset state RESET = 0 Reset state RESET = 1 RESET = 1, MRESET = 1 Exception-handling state Bus request Bus request clearance...
Page 89 Rev. 3.0, 04/02, page 50 of 1064...
Page 90: Memory Management Unit (Mmu)
(translation lookaside buffer: TLB). The SH7751 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte).
Page 91 (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7751 Series is referred to as virtual address space, and the address space in physical memory as physical address space.
Page 92: Figure 3.1 Role Of The Mmu
Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev. 3.0, 04/02, page 53 of 1064...
Page 93: Register Configuration
3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Name tion Value* Address* Address* Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register Page table entry low PTEL Undefined H'FF00 0004 H'1F00 0004 32...
Page 94: Register Descriptions
Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.
Page 95 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware.
Page 96 Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction.
Page 97: Address Space
3.3.1 Physical Address Space The SH7751 Series supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3.
Page 98: Figure 3.3 Physical Address Space (Mmucr.at = 0)
P4 Area: The P4 area is mapped onto SH7751 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4.
Page 99: Figure 3.4 P4 Area
H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000 Operand cache data array H'F600 0000...
Page 100: External Memory Space
3.3.2 External Memory Space The SH7751 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC).
Page 101: Virtual Address Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in the SH7751 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1- Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.