Hitachi SH7751 Hardware Manual

Superh risc engine

page of 1104

/ 1104
Contents
Table of Contents
Bookmarks

Quick Links

Download this manual

To all our customers

Regarding the change of names mentioned in the document, such as

Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were

transferred to Renesas Technology Corporation on April 1st 2003.

These operations include microcomputer, logic, analog and discrete devices,

and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,

and other Hitachi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp.

Thank you for your understanding. Except for our corporate trademark,

logo and corporate statement, no changes whatsoever have been made to the

contents of the document, and these changes do not constitute any alteration

to the contents of the document itself.

Renesas Technology Corp.

Renesas Technology Home Page: www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

Table of Contents

Related Manuals for Hitachi SH7751

Engine Hitachi SH7750 Hardware Manual
Sh7750 series superh risc engine (1037 pages)
Engine Hitachi SH7750 Programming Manual
High-performance risc engine superh (sh) 32-bit risc mcu/mpu series (412 pages)

Engine Hitachi SH7750 series Hardware Manual
Superh risc engine (858 pages)

Summary of Contents for Hitachi SH7751

Page 1 DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark,...
Page 2 Hitachi SuperH RISC engine SH7751 Series SH7751, SH7751R Hardware Manual ADE-602-201B Rev. 3.0 4/11/2002 Hitachi, Ltd.
Page 3 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7751 Series is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and PCI controller (PCIC).
Page 5 User manuals for SH7751 and SH7751R Name of Document Document No. SH7751 Series Hardware Manual This manual SH-4 Programming Manual ADE-602-156 User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual...
Page 6: Table Of Contents
Contents Section 1 Overview ......................SH7751 Series Features..................... Block Diagram ........................10 Pin Arrangement ....................... 11 Pin Functions........................13 1.4.1 Pin Functions (256-Pin QFP) ................13 1.4.2 Pin Functions (256-Pin BGA) ................24 Section 2 Programming Model ..................35 Data Formats ........................35 Register Configuration ......................
Page 7 3.4.2 Instruction TLB (ITLB) Configuration ..............69 3.4.3 Address Translation Method ................69 MMU Functions ........................ 72 3.5.1 MMU Hardware Management ................72 3.5.2 MMU Software Management................72 3.5.3 MMU Instruction (LDTLB) ................. 72 3.5.4 Hardware ITLB Miss Handling................73 3.5.5 Avoiding Synonym Problems ................
Page 8 Memory-Mapped Cache Configuration (SH7751) ............103 4.5.1 IC Address Array ....................103 4.5.2 IC Data Array ....................... 104 4.5.3 OC Address Array ....................105 4.5.4 OC Data Array ..................... 106 Memory-Mapped Cache Configuration (SH7751R) ............107 4.6.1 IC Address Array ....................108 4.6.2...
Page 9 Data Formats ........................155 6.2.1 Floating-Point Format ..................155 6.2.2 Non-Numbers (NaN).................... 157 6.2.3 Denormalized Numbers..................158 Registers ..........................159 6.3.1 Floating-Point Registers ..................159 6.3.2 Floating-Point Status/Control Register (FPSCR) ..........161 6.3.3 Floating-Point Communication Register (FPUL)..........162 Rounding ........................... 162 Floating-Point Exceptions ....................
Page 10 9.5.1 Transition to Pin Sleep Mode................225 9.5.2 Exit from Pin Sleep Mode ..................225 Standby Mode ........................225 9.6.1 Transition to Standby Mode ................. 225 9.6.2 Exit from Standby Mode ..................226 9.6.3 Clock Pause Function................... 227 Module Standby Function ....................227 9.7.1 Transition to Module Standby Function...............
Page 11 10.8.3 Notes on Register Access ..................257 10.9 Using the WDT ......................... 258 10.9.1 Standby Clearing Procedure................. 258 10.9.2 Frequency Changing Procedure ................258 10.9.3 Using Watchdog Timer Mode................259 10.9.4 Using Interval Timer Mode.................. 259 10.10 Notes on Board Design...................... 260 Section 11 Realtime Clock (RTC) ..................
Page 12 Section 12 Timer Unit (TMU) ..................287 12.1 Overview ........................... 287 12.1.1 Features ........................ 287 12.1.2 Block Diagram ..................... 288 12.1.3 Pin Configuration ....................288 12.1.4 Register Configuration ..................289 12.2 Register Descriptions......................290 12.2.1 Timer Output Control Register (TOCR) .............. 290 12.2.2 Timer Start Register (TSTR) ................
Page 13 .......... 463 14.1 Overview ........................... 463 14.1.1 Features ........................ 463 14.1.2 Block Diagram (SH7751)..................466 14.1.3 Pin Configuration (SH7751) ................467 14.1.4 Register Configuration (SH7751) ................ 468 14.2 Register Descriptions......................470 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........... 470 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) ........471 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......
Page 14 14.4.1 Examples of Transfer between External Memory and an External Device with DACK ......................519 14.5 On-Demand Data Transfer Mode (DDT Mode) ..............520 14.5.1 Operation......................520 14.5.2 Pins in DDT Mode ....................522 14.5.3 Transfer Request Acceptance on Each Channel........... 525 14.5.4 Notes on Use of DDT Module ................
Page 15 15.3.2 Operation in Asynchronous Mode................ 599 15.3.3 Multiprocessor Communication Function ............609 15.3.4 Operation in Synchronous Mode................618 15.4 SCI Interrupt Sources and DMAC..................627 15.5 Usage Notes........................628 Section 16 Serial Communication Interface with FIFO (SCIF) ......633 16.1 Overview ........................... 633 16.1.1 Features ........................
Page 16 17.3.1 Overview ......................686 17.3.2 Pin Connections....................687 17.3.3 Data Format......................688 17.3.4 Register Settings....................689 17.3.5 Clock ........................691 17.3.6 Data Transfer Operations ..................694 17.4 Usage Notes........................701 Section 18 I/O Ports ......................707 18.1 Overview ........................... 707 18.1.1 Features ........................
Page 17 20.6.1 Transition to User Break Controller Stopped State ..........775 20.6.2 Cancelling the User Break Controller Stopped State ........... 775 20.6.3 Examples of Stopping and Restarting the User Break Controller ......776 Section 21 Hitachi User Debug Interface (H-UDI) ............ 777 21.1 Overview ........................... 777 21.1.1 Features ........................
Page 18 21.1.3 Pin Configuration ....................779 21.1.4 Register Configuration ..................780 21.2 Register Descriptions......................781 21.2.1 Instruction Register (SDIR).................. 781 21.2.2 Data Register (SDDR)..................782 21.2.3 Bypass Register (SDBPR)..................782 21.2.4 Interrupt Factor Register (SDINT) ............... 783 21.2.5 Boundary Scan Register (SDBSR) ............... 783 21.3 Operation...........................
Page 19 22.2.21 PCI Interrupt Mask Register (PCIINTM)............. 848 22.2.22 PCI Address Data Register at Error (PCIALR)............ 850 22.2.23 PCI Command Data Register at Error (PCICLR)..........851 22.2.24 PCI Arbiter Interrupt Register (PCIAINT)............853 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM) ..........855 22.2.26 PCI Error Bus Master Data Register (PCIBMLR) ..........
Page 20 22.6.2 Interrupts from External PCI Devices ..............921 22.6.3 ........................921 22.7 Error Detection ........................922 22.8 PCIC Clock ........................922 22.9 Power Management......................923 22.9.1 Power Management Overview ................923 22.9.2 Stopping the Clock ....................924 22.9.3 Compatibility with Standby and Sleep ..............927 22.10 Port Functions ........................
Page 21 Figures Figure 1.1 Block Diagram of SH7751 Series Functions ........... Figure 1.2 Pin Arrangement (256-Pin QFP)..............Figure 1.3 Pin Arrangement (256-Pin BGA) ..............Figure 2.1 Data Formats....................Figure 2.2 CPU Register Configuration in Each Processor Mode ........Figure 2.3 General Registers .....................
Page 22 Timing When Power Other than VDD-RTC is Off ......... 239 Figure 9.15 Timing When VDD-RTC Power is Off On ..........240 Figure 10.1(1) Block Diagram of CPG (SH7751) ..............243 Figure 10.1(2) Block Diagram of CPG (SH7751R)..............244 Figure 10.2 Block Diagram of WDT................... 253 Figure 10.3...
Page 23 Figure 12.7 Operation Timing when Using Input Capture Function........302 Figure 13.1 Block Diagram of BSC ..................307 Figure 13.2 Correspondence between Virtual Address Space and External Memory Space 311 Figure 13.3 External Memory Space Allocation ..............313 Figure 13.4 Example of Sampling Timing at which BCR4 is Set (Two Wait Cycles are Inserted by WCR2) ............
Page 24 Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle ..................... 410 Figure 13.35 Auto-Refresh Operation................... 411 Figure 13.36 Synchronous DRAM Auto-Refresh Timing ............ 412 Figure 13.37 Synchronous DRAM Self-Refresh Timing ............413 Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL) ......... 415 Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ....
Page 25 Figure 13.62 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................445 Figure 13.63 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................
Page 26 Figure 14.15 Dual Address Mode/Burst Mode External Bus External Bus/ (Edge Detection), DACK (Read Cycle) ..........508 Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) External Bus..................... 509 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus On-Chip SCI (Level Detection) .....................
Page 27 Figure 14.40 Write to Synchronous DRAM (Row Hit) ............536 Figure 14.41 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ........537 Figure 14.42 DDT Mode Setting................... 538 Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device External Bus Data Transfer................
Page 28 Figure 15.10 Sample Serial Reception Flowchart (1) ............606 Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ....................609 Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)........610 Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart........
Page 29 Figure 17.7 Sample Initialization Flowchart ............... 695 Figure 17.8 Sample Transmission Processing Flowchart............ 697 Figure 17.9 Sample Reception Processing Flowchart ............699 Figure 17.10 Receive Data Sampling Timing in Smart Card Mode........701 Figure 17.11 Retransfer Operation in SCI Receive Mode............. 702 Figure 17.12 Retransfer Operation in SCI Transmit Mode ...........
Page 30 Figure 22.19 Endian Control for Local Bus ................912 Figure 22.20 Data Alignment at DMA Transfer ..............913 Figure 22.21(1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) .... 915 Figure 22.21(2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus)..916 Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) .
Page 31 Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) ...... 981 Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)......982 Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD [1:0] = 01, TRWL [2:0] = 010)............
Page 32 Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001, TRC [2:0] = 001) ............. 1004 Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001)......1005 Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait........................
Page 33 Figure 23.67 H-UDI Data Transfer Timing ................1021 Figure 23.68 Pin Break Timing..................... 1021 Figure 23.69 NMI Input Timing ................... 1022 Figure 23.70 PCI Clock Input Timing................... 1025 Figure 23.71 Output Signal Timing ..................1025 Figure 23.72 Output Signal Timing ..................1026 Figure 23.73 I/O Port Input/Output Timing ................
Page 34 State of Registers in Standby Mode ..............226 Table 10.1 CPG Pins ......................246 Table 10.2 CPG Register...................... 246 Table 10.3(1) Clock Operating Modes (SH7751)..............247 Table 10.3(2) Clock Operating Modes (SH7751R) ..............247 Table 10.4 FRQCR Settings and Internal Clock Frequencies ..........248 Table 10.5 WDT Registers....................
Page 35 Table 13.14 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing 379 Table 13.15 Example of Correspondence between SH7751 Series and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0) ..395 Table 13.16 Cycles in Which Pipelined Access Can Be Used ..........409 Table 13.17...
Page 36 Table 15.2 SCI Registers...................... 572 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ..... 591 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode....594 Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)..................
Page 37 Table 21.3 Structure of Boundary Scan Register ..............784 Table 22.1 Pin Configuration ....................804 Table 22.2 List of PCI Configuration Registers ..............806 Table 22.3 PCI Configuration Register Configuration............807 Table 22.4 List of PCIC Local Registers................808 Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)......
Page 38 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) ................... 1027 Table A.1 Address List......................1031 Table C.1 Clock Operating Modes (SH7751)..............1041 Table C.2 Clock Operating Modes (SH7751R) ..............1041 Table C.3 Area 0 Memory Map and Bus Width ..............1042 Table C.4...
Page 39 Rev. 3.0, 04/02, page xxxviii of xxxviii...
Page 40: Section 1 Overview
50% reduction in program size over a 32-bit instruction set. The SH7751 Series feature the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751 Series have an instruction cache, an...
Page 41: Figure 13.61 Mpx Interface Timing
Table 1.1 SH7751 Series Features Item Features Operating frequency: 240 MHz* /200 MHz* /167 MHz* /133 MHz* Performance: 430 MIPS (240 MHz), 360 MIPS (200 MHz) 300 MIPS (167 MHz), 240 MIPS (133 MHz) 1.2 GFLOPS (167 MHz), 0.93 GFLOPS (133 MHz) 1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz)
Page 42 Table 1.1 SH7751 Series Features (cont) Item Features Original Hitachi SuperH architecture 32-bit internal data bus General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers RISC-type instruction set (upward-compatible with SuperH Series)
Page 43 Table 1.1 SH7751 Series Features (cont) Item Features On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt...
Page 44 Clock pulse Choice of main clock generator (CPG) SH7751: 1/2, 1, 3, or 6 times EXTAL SH7751R: 1, 6, or 12 times EXTAL Clock modes: (Maximum frequency: Varies with models) CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock...
Page 45 [SH7751R] 16 kbytes, 2-way set associative 256 entries/way, 32-byte block length Cache-double-mode (16-kbyte cache) Index mode SH7751-compatible mode (8 kbytes, direct mapping) Operand cache (OC) 32 kbytes, 2-way set associative 512 entries/way, 32-byte block length Cache-double-mode (32-kbyte cache) Index mode...
Page 46 Table 1.1 SH7751 Series Features (cont) Item Features Interrupt controller Five independent external interrupts (NMI, IRL3 to IRL0) (INTC) 15-level signed external interrupts: IRL3 to IRL0 On-chip peripheral module interrupts: Priority level can be set for each module User break...
Page 47 Table 1.1 SH7751 Series Features (cont) Item Features Direct memory Physical address DMA controller access controller SH7751: 4-channel (DMAC) SH7751R: 8-channel Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes Address modes: 1-bus-cycle single address mode 2-bus-cycle dual address mode...
Page 48 Table 1.1 SH7751 Series Features (cont) Item Features PCI bus controller PCI bus controller (Rev.2.1-compatible)* (PCIC) 32-bit bus 33 MHz/66 MHz support PCI master/slave support PCI host function support Built-in bus arbiter 4 built-in PCI-dedicated DMAC (direct memory access controller)
Page 49: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram of the SH7751 Series. Lower 32-bit data Cache and I cache ITLB UTLB O cache controller INTC DMAC (SCIF) PCIC (PCI)DMAC BSC: Bus state controller CPG: Clock pulse generator DMAC: Direct memory access controller...
Page 50: Pin Arrangement
Pin Arrangement XTAL2 EXTAL2 VDD-RTC VSS-RTC PCICLK IDSEL /MD9 /MD10 MD6/ MD2/RXD2 QFP256 TCLK MD8/ MD1/TXD2 MD0/SCK2 MD7/ (Top view) AUDSYNC AUDCK AUDATA0 AUDATA1 AUDATA2 AUDATA3 Reserved MD3/ MD4/ VDD (internal) DACK0 VSS (internal) DACK1 DRAK0 DRAK1 VDDQ (IO) STATUS0 VSSQ (IO) STATUS1 /BRKACK...
Page 51: Figure 1.3 Pin Arrangement (256-Pin Bga)
BGA256 (Top view) VDDQ(IO) VSS (internal) VDD-CPG/RTC VSSQ(IO) VSS-CPG/RTC VDD-PLL1/2 VDD (internal) VSS-PLL1/2 Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * May be connected to V Figure 1.3 Pin Arrangement (256-Pin BGA) Rev.
Page 52: Pin Functions
Pin Functions 1.4.1 Pin Functions (256-Pin QFP) Table 1.2 Pin Functions Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND Data in (H-UDI) Chip select 0 Chip select 1 Chip select 4 ...
Page 53 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data D7–D0 DQM0 DQM0 select signal D15–D8...
Page 54 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND Address Address Address Address...
Page 55 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD Power Internal GND Address 100 A19 Address...
Page 56 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus grant (host function) Bus request (host function) Bus request MD10 MD10 (host function)/ mode 119 VDDQ Power IO VDD 120 VSSQ Power IO GND ...
Page 57 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 134 AD28 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 135 AD27 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 136 AD26 PCI address/ (Port) (Port) (Port)
Page 58 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Device select 157 VDDQ Power IO VDD 158 VSSQ Power IO GND Transaction stop Exclusive access Parity error 162 PAR Parity 163 C/ Command/...
Page 59 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 179 AD5 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 180 AD4 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 181 AD3 PCI address/ (Port) (Port) (Port)
Page 60 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX acknowledge/ bus request request/bus acknowledge 204 MD6/ Mode/ (PCMCIA) Bus ready 206 TXD SCI data output 207 VDDQ Power IO VDD 208 VSSQ...
Page 61 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 225 VDD Power Internal VDD 226 VSS Power Internal GND 227 AUDATA2 AUD data 228 AUDATA3 AUD data 229 Reserved Do not connect 230 MD3/...
Page 62 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 247 VDDQ Power IO VDD 248 VSSQ Power IO GND 249 VDD-PLL2 Power PLL2 VDD 250 VSS-PLL2 Power PLL2 GND 251 VDD-PLL1 Power PLL1 VDD 252 VSS-PLL1 Power PLL1 GND 253 VDD-CPG...
Page 63: Pin Functions (256-Pin Bga)
1.4.2 Pin Functions (256-Pin BGA) Table 1.3 Pin Functions Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND Data in (H-UDI) Chip select 0 Chip select 1 Chip select 4 Chip select 5...
Page 64 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data D7–D0 DQM0 DQM0 select signal D15–D8 DQM1 DQM1 select signal...
Page 65 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND Address Address Address Address ...
Page 66 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD Power Internal GND Address Address Address...
Page 67 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Bus grant (host function) Bus request (host function) Bus request MD10 MD10 (host function)/ mode VDDQ Power IO VDD VSSQ Power IO GND Bus request...
Page 68 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AD26 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD25 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD24 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port...
Page 69 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Transaction stop Exclusive access Parity error Parity Command/ byte enable AD15 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD14...
Page 70 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port VDDQ Power I/O VDD...
Page 71 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA request/bus acknowledge MD6/ Mode/ (PCMCIA) Bus ready SCI data output VDDQ Power IO VDD VSSQ Power IO GND Power Internal VDD Power Internal GND...
Page 72 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AUDATA2 AUD data AUDATA3 AUD data Do not connect MD3/ Mode/ PCMCIA-CE MD4/ Mode/ PCMCIA-CE Mode VDDQ Power IO VDD VSSQ Power IO GND...
Page 73 Table 1.3 Pin Functions (cont) Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSS-PLL2 Power PLL2 GND VDD-PLL1 Power PLL1 VDD VSS-PLL1 Power PLL1 GND VDD-CPG Power CPG VDD VSS-CPG Power CPG GND XTAL Crystal resonator EXTAL External input clock/crystal resonator...
Page 74: Section 2 Programming Model
Section 2 Programming Model Data Formats The data formats handled by the SH7751 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 75: Register Configuration
Processor Modes: The SH7751 Series has two processor modes, user mode and privileged mode. The SH7751 Series normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be...
Page 76: Table 2.1 Initial Register Values
Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.
Page 77: Figure 2.2 Cpu Register Configuration In Each Processor Mode
R0 _ BANK0* R0 _ BANK1* R0 _ BANK0* R1 _ BANK0* R1 _ BANK0* R1 _ BANK1* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK1* R3 _ BANK0* R4 _ BANK0* R4 _ BANK0* R4 _ BANK1* R5 _ BANK0* R5 _ BANK1*...
Page 78: General Registers
R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7751 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
Page 79: Figure 2.3 General Registers
SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...
Page 80: Floating-Point Registers
2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Page 81: Figure 2.4 Floating-Point Registers
Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0...
Page 82: Control Registers
Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X = undefined)) 31 30 29 28 27 16 15 14 —...
Page 83: System Registers
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 84 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15;...
Page 85: Memory-Mapped Registers
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 86: Data Format In Registers
Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Longword Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.
Page 87: Processor States
Note: The SH7751 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. Processor States The SH7751 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state.
Page 88: Processor Modes
From any state when From any state when RESET = 0 RESET = 1 and MRESET = 0 Power-on reset state Manual reset state RESET = 0 Reset state RESET = 1 RESET = 1, MRESET = 1 Exception-handling state Bus request Bus request clearance...
Page 89 Rev. 3.0, 04/02, page 50 of 1064...
Page 90: Memory Management Unit (Mmu)
(translation lookaside buffer: TLB). The SH7751 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte).
Page 91 (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7751 Series is referred to as virtual address space, and the address space in physical memory as physical address space.
Page 92: Figure 3.1 Role Of The Mmu
Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev. 3.0, 04/02, page 53 of 1064...
Page 93: Register Configuration
3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Name tion Value* Address* Address* Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register Page table entry low PTEL Undefined H'FF00 0004 H'1F00 0004 32...
Page 94: Register Descriptions
Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.
Page 95 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware.
Page 96 Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction.
Page 97: Address Space
3.3.1 Physical Address Space The SH7751 Series supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3.
Page 98: Figure 3.3 Physical Address Space (Mmucr.at = 0)
P4 Area: The P4 area is mapped onto SH7751 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4.
Page 99: Figure 3.4 P4 Area
H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000 Operand cache data array H'F600 0000...
Page 100: External Memory Space
3.3.2 External Memory Space The SH7751 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC).
Page 101: Virtual Address Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in the SH7751 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1- Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.
Page 102: On-Chip Ram Space
3.3.4 On-Chip RAM Space In the SH7751 Series, half of the operand cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0, U0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area.
Page 103: Single Virtual Memory Mode And Multiple Virtual Memory Mode
Notes: (1) In single virtual memory mode of the SH7751 Series, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously.
Page 104: Tlb Functions
UTLB with a different ASID and unshared address translation information. Note that this restriction does not apply to the SH7751R. TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1.
Page 105: Figure 3.8 Relationship Between Page Size And Address Format
• 1-kbyte page Virtual address Physical address 10 9 10 9 Offset Offset • 4-kbyte page Virtual address Physical address 12 11 12 11 Offset Offset • 64-kbyte page Virtual address Physical address 16 15 16 15 Offset Offset • 1-Mbyte page Virtual address Physical address 20 19...
Page 106 SZ: Page size bits Specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-Mbyte page V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset.
Page 107 D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0.
Page 108: Instruction Tlb (Itlb) Configuration
3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries.
Page 109: Figure 3.10 Flowchart Of Memory Access Using Utlb
Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match...
Page 110: Figure 3.11 Flowchart Of Memory Access Using Itlb
Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match VPNs match...
Page 111: Mmu Functions
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7751 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.
Page 112: Hardware Itlb Miss Handling
3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7751 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB.
Page 113: Avoiding Synonym Problems
This problem does not occur with the instruction TLB or instruction cache. In the SH7751 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4- kbyte page, are subject to address translation.
Page 114: Mmu Exceptions
MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 115: Instruction Tlb Protection Violation Exception
Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3.
Page 116: Data Tlb Multiple Hit Exception
Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3.
Page 117: Data Tlb Miss Exception
3.6.5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1.
Page 118: Data Tlb Protection Violation Exception
3.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below.
Page 119: Memory-Mapped Tlb Configuration
3. Sets exception code H'080 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC.
Page 120: Itlb Address Array
performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 121: Itlb Data Array 1
3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.
Page 122: Itlb Data Array 2
3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 123: Figure 3.16 Memory-Mapped Utlb Address Array
In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0].
Page 124: Utlb Data Array 1
3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field.
Page 125: Utlb Data Array 2
3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 126: Section 4 Caches
RAM. When the EMODE bit in the CCR register is cleared to 0 in the SH7751R, both the IC and OC are set to SH7751 compatible mode. Operation is as shown in table 4.1. When the EMODE bit in the CCR register is set to 1, the cache characteristics are as shown in table 4.2.
Page 127: Register Configuration
Table 4.2 Cache Features (SH7751R) Item Instruction Cache Operand Cache Capacity 16-kbyte cache 32-kbyte cache or 16-kbyte cache + 16-kbyte RAM Type 2-way set-associative 2-way set-associative Line size 32 bytes 32 bytes Entries 256 entry/way 512 entry/way Write method Copy-back/write-through selectable Replace method LRU (Least Recently Used) LRU (Least Recently Used)
Page 128: Register Descriptions
0 must be specified in a write; the read value is 0. Figure 4.1 Cache and Store Queue Control Registers (CCR) (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: Cache-double-mode (SH7751R only. Reserved bit in SH7751.) IIX: IC index enable...
Page 129 EMODE: Cache-double-mode bit Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in the SH7751. The EMODE bit cannot be modified while the cache is in use. 0: SH7751-compatible-mode (Initial value) 1: Cache-double-mode Note: *1 Address allocation in OC index mode and RAM mode is not compatible with that in RAM mode.
Page 130: Operand Cache (Oc)
4.3.1 Configuration The operand cache in the SH7751 adopts the direct-mapping method, and consists of 512 cache lines. Each cache line is composed of a 19-bit tag, V bit, U bit, and 32-byte data. The operand cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 512 cache lines.
Page 131: Figure 4.2 Configuration Of Operand Cache (Sh7751)
1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Write data Read data Hit signal Figure 4.2 Configuration of Operand Cache (SH7751) Rev. 3.0, 04/02, page 92 of 1064...
Page 132: Figure 4.3 Configuration Of Operand Cache (Sh7751R)
Effective address 26 25 13 12 RAM area Longword (LW) determination selection [12:5] [13] Entry selection Address array Data array (way 0, way 1) (way 0, way 1) 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits...
Page 133: Read Operation
The U bit is never set to 1 while the cache is being used in write- through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, Memory-Mapped Cache Configuration (SH7751) and 4.6, Memory-Mapped Cache Configuration (SH7751R)). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Page 134: Write Operation
3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU.
Page 135 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data field of the cache line indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. A write is also performed to the corresponding external memory using the specified access size.
Page 136: Write-Back Buffer
Setting CCR.ORA to 1 enables 8 kbytes of the operand cache to be used as RAM. The operand cache entries used as RAM are the 8 kbytes of entries 128 to 255 and 384 to 511. In SH7751- compatible-mode in the SH7751R, the 8 kbytes of operand cache entries 256 to 511 are used as RAM.
Page 137 H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-kbyte RAM area. An example of RAM use in the SH7751R is shown below. SH7751-compatible-mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area (entries 256 to 511) A shadow of the RAM area occurs every 8 kbytes up to H'7FFF FFFF.
Page 138: Oc Index Mode
Prefetch Operation The SH7751 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance.
Page 139: Figure 4.6 Configuration Of Instruction Cache (Sh7751)
Figure 4.6 shows the configuration of the instruction cache in the SH7751. Figure 4.7 shows the configuration of the instruction cache in the SH7751R. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 [11:5] [12]...
Page 140: Figure 4.7 Configuration Of Instruction Cache (Sh7751R)
Effective address 13 12 11 10 Longword (LW) selection [11:5] [12] Entry selection Address array (way 0, way 1) Data array (way 0, way 1) 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit...
Page 141: Read Operation
LRU (SH7751R only) In a 2-way set-associative system, up to two entry addresses (among addresses 12 to 15) can register the same data in cache. The LRU bit indicates to which way the entry is to be registered among the two ways. There is one LRU bit in each entry, and it is controlled by hardware.
Page 142: Memory-Mapped Cache Configuration (Sh7751)
Memory-Mapped Cache Configuration (SH7751) To enable the IC and OC to be managed by software, the IC contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area.
Page 143: Ic Data Array
MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed.
Page 144: Oc Address Array
2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2 1 0 Address field 1 1 1 1 0 0 0 1...
Page 145: Oc Data Array
the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after write- back of that cache line, the tag, U bit, and V bit specified in the data field are written.
Page 146: Memory-Mapped Cache Configuration (Sh7751R)
Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified, and read values are undefined. Note that the memory-mapped cache configuration in SH7751-compatible-mode of the SH7751R is the same as that in the SH7751. Rev. 3.0, 04/02, page 107 of 1064...
Page 147: Ic Address Array
4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag and V bit are specified in the data field.
Page 148: Ic Data Array
5 4 3 2 1 0 Address field 1 1 1 1 0 0 0 0 Entry 10 9 Data field : Validity bit : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area.
Page 149: Oc Address Array
2 1 0 Address field 1 1 1 1 0 0 0 1 Entry Data field Longword data : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area.
Page 150: Oc Data Array
3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, each way’s tag stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set in bit [14] is ignored.
Page 151: Summary Of Memory-Mapped Oc Addresses
The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field.
Page 152: Store Queues
Store Queues Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory. When not using the SQs, the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.
Page 153 External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In the SH7751 Series, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register.
Page 154: Determination Of Sq Access Exception
If an exception occurs in an SQ write, the SQ contents may be corrupted in the SH7751 (see section 4.7.6, SQ Usage Notes), but the previous values of the SQ contents are guaranteed in the SH7751R. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted.
Page 155: Sq Usage Notes
If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7751, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs.
Page 156 Example 3: When an instruction at which an exception occurs is a branch instruction but a branch is not made Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ;...
Page 157 Rev. 3.0, 04/02, page 118 of 1064...
Page 158: Section 5 Exceptions
SH7751 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1.
Page 159: Register Descriptions
Register Descriptions There are three registers related to exception handling. Addresses are allocated for these, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.
Page 160: Exception Handling Functions
Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR) and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register 15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 161: Exception Types And Priorities
Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Reset Abort type Power-on reset H'A000 0000 —...
Page 162 Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340...
Page 163 Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral H-UDI H-UDI (VBR) H'600 H'600 type module GPIO GPIOI H'620 interrupt DMAC DMTE0 H'640 (module/ source) DMTE1 H'660 DMTE2 H'680 DMTE3 H'6A0...
Page 164: Exception Flow
Exception Flow 5.5.1 Exception Flow Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt).
Page 165: Exception Source Acceptance
5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline.
Page 166: Figure 5.3 Example Of General Exception Acceptance Order
Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Instruction fetch ID: Instruction decode EX: Instruction execution Instruction n+3 MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling:...
Page 167: Exception Requests And Bl Bit
5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU’s internal registers and the registers of the other modules are set to their post-reset state, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 168: Resets
5.6.1 Resets (1) Power-On Reset Sources: pin low level When the watchdog timer overflows while the WT/ bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. Transition address: H'A000 0000 Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a...
Page 169: Table 5.3 Types Of Reset
(2) Manual Reset Sources: pin low level and pin high level When a general exception other than a user break occurs while the BL bit is set to 1 in SR When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
Page 170 (3) H-UDI Reset Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) Transition address: H'A000 0000 Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111.
Page 171 (4) Instruction TLB Multiple-Hit Exception Source: Multiple ITLB address matches Transition address: H'A000 0000 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 172 (5) Data TLB Multiple-Hit Exception Source: Multiple UTLB address matches Transition address: H'A000 0000 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 173: General Exceptions
5.6.2 General Exceptions (1) Data TLB Miss Exception Source: Address mismatch in UTLB address comparison Transition address: VBR + H'0000 0400 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 174 (2) Instruction TLB Miss Exception Source: Address mismatch in ITLB address comparison Transition address: VBR + H'0000 0400 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 175 (3) Initial Page Write Exception Source: TLB is hit in a store access, but dirty bit D = 0 Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 176 (4) Data TLB Protection Violation Exception Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible Read/write access possible...
Page 177 (5) Instruction TLB Protection Violation Exception Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 178 (6) Data Address Error Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) Access to area H'8000 0000–H'FFFF FFFF in user mode Transition address: VBR + H'0000 0100...
Page 179 (7) Instruction Address Error Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 180 (8) Unconditional Trap Source: Execution of TRAPA instruction Transition address: VBR + H'0000 0100 Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 181 (9) General Illegal Instruction Exception Sources: Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR Transition address: VBR + H'0000 0100...
Page 182 (10) Slot Illegal Instruction Exception Sources: Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR Decoding in user mode of a privileged instruction in a delay slot...
Page 183 (11) General FPU Disable Exception Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 Transition address: VBR + H'0000 0100 Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 184 (12) Slot FPU Disable Exception Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 Transition address: VBR + H'0000 0100 Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 185 (13) User Breakpoint Trap Source: Fulfilling of a break condition set in the user break controller Transition address: VBR + H'0000 0100, or DBR Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 186 (14) FPU Exception Source: Exception due to execution of a floating-point operation Transition address: VBR + H'0000 0100 Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in EXPEVT.
Page 187: Interrupts
5.6.3 Interrupts (1) NMI Source: NMI pin edge detection Transition address: VBR + H'0000 0600 Transition operations: The PC and SR contents for the instruction at which this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 188 (2) IRL Interrupts Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). Transition address: VBR + H'0000 0600 Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC.
Page 189 (3) Peripheral Module Interrupts Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, PCIC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). Transition address: VBR + H'0000 0600 Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in...
Page 190: Priority Order With Multiple Exceptions
5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 191: Usage Notes
If the accepted exception (the highest-priority exception) is a delay slot instruction re- execution type exception, the branch instruction PR register write operation (PC operation performed in BSR, BSRF, JSR) is not inhibited. Usage Notes 1. Return from exception handling a.
Page 192: Restrictions
Restrictions 1. Restrictions on first instruction of exception handling routine Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register.
Page 193 Rev. 3.0, 04/02, page 154 of 1064...
Page 194: Section 6 Floating-Point Unit
A floating-point number consists of the following three fields: Sign (s) Exponent (e) Fraction (f) The SH7751 Series can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 23 22 Figure 6.1 Format of Single-Precision Floating-Point Number...
Page 195: Figure 6.2 Format Of Double-Precision Floating-Point Number
52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1. The two values E –...
Page 196: Non-Numbers (Nan)
Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000000 Positive normalized H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to number H'00100000 00000000 Positive denormalized...
Page 197: Denormalized Numbers
EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7751 Series as operation results are as follows: Single-precision qNaN: H'7FBFFFFF...
Page 198: Registers
Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;...
Page 199: Figure 6.4 Floating-Point Registers
FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14 FPR15_BANK0 FR15 XF15 FPR0_BANK1...
Page 200: Floating-Point Status/Control Register (Fpscr)
6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15;...
Page 201: Floating-Point Communication Register (Fpul)
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occurred, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 202: Floating-Point Exceptions
0, but the corresponding bit in the FPU exception flag field remains unchanged. Enable/disable exception handling The SH7751 Series supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases: FPU error (E): FPSCR.DN = 0 and a denormalized number is input Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)
Page 203: Graphics Support Functions
The number of significant digits is 24 for a normalized number and 23 for a denormalized number (number of leading zeros in the fractional part). In future version of SuperH series, the above error is guaranteed, but the same result as SH7751 Series is not guaranteed.
Page 204 This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 4 matrix, the SH7751 Series supports 4-dimensional operations. Matrix (4 matrix (4 This operation requires the execution of four FTRV instructions.
Page 205: Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, the SH7751 Series also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the SH7751 Series can perform data transfer by means of pair single- precision data transfer instructions. FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14;...
Page 206: Section 7 Instruction Set
Execution Environment PC: PC indicates the address of the instruction itself. Data sizes and data types: The SH7751 Series instruction set is implemented with 16-bit fixed- length instructions. The SH7751 Series can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access.
Page 207 In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution.
Page 208: Addressing Modes
Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 209 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + indirect with 4-bit displacement disp added. After disp is disp displacement zero-extended, it is multiplied by 1 (byte), 2 (word),...
Page 210 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 with disp added. After disp is zero-extended, it is + disp displacement multiplied by 2 (word), or 4 (longword), according...
Page 211: Table 7.1 Addressing Modes And Effective Addresses
Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp disp added after being sign-extended and Branch- multiplied by 2. Target PC + 4 + disp ×...
Page 212: Instruction Set
Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand Summary of Transfer direction operation (xx):...
Page 213: Table 7.3 Fixed-Point Transfer Instructions
Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit #imm,Rn sign extension 1110nnnniiiiiiii — — MOV.W @(disp,PC),Rn (disp 2 + PC + 4) sign 1001nnnndddddddd — — extension MOV.L @(disp,PC),Rn (disp 4 + PC & H'FFFFFFFC 1101nnnndddddddd — —...
Page 214 Table 7.3 Fixed-Point Transfer Instructions (cont) Instruction Operation Instruction Code Privileged T Bit MOV.B R0,@(disp,GBR) (disp + GBR) 11000000dddddddd — — MOV.W R0,@(disp,GBR) (disp 2 + GBR) 11000001dddddddd — — MOV.L R0,@(disp,GBR) (disp 4 + GBR) 11000010dddddddd — — MOV.B @(disp,GBR),R0 (disp + GBR) 11000100dddddddd —...
Page 215 Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rm,Rn Rn + Rm 0011nnnnmmmm1100 — — #imm,Rn Rn + imm 0111nnnniiiiiiii — — ADDC Rm,Rn Rn + Rm + T Rn, carry 0011nnnnmmmm1110 — Carry ADDV Rm,Rn Rn + Rm Rn, overflow 0011nnnnmmmm1111 —...
Page 216: Table 7.4 Arithmetic Operation Instructions
Table 7.4 Arithmetic Operation Instructions (cont) Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 — — word MAC.L @Rm+,@Rn+ Signed, (Rn) (Rm) + MAC...
Page 217: Table 7.5 Logic Operation Instructions
Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rm,Rn Rn & Rm 0010nnnnmmmm1001 — — #imm,R0 R0 & imm 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm (R0 + 11001101iiiiiiii — — GBR) Rm,Rn 0110nnnnmmmm0111 —...
Page 218: Table 7.6 Shift Instructions
Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit ROTL 0100nnnn00000100 — ROTR 0100nnnn00000101 — ROTCL 0100nnnn00100100 — ROTCR 0100nnnn00100101 — SHAD Rm,Rn When Rn 0, Rn << Rm 0100nnnnmmmm1100 — — When Rn < 0, Rn >> Rm [MSB SHAL 0100nnnn00100000 —...
Page 219: Table 7.7 Branch Instructions
Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit label When T = 0, disp 2 + PC + 10001011dddddddd — — When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd — — disp 2 + PC + 4 When T = 1, nop...
Page 220: Table 7.8 System Control Instructions
Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit CLRMAC MACH, MACL 0000000000101000 — — CLRS 0000000001001000 — — CLRT 0000000000001000 — Rm,SR 0100mmmm00001110 Privileged Rm,GBR 0100mmmm00011110 — — Rm,VBR 0100mmmm00101110 Privileged — Rm,SSR 0100mmmm00111110 Privileged — Rm,SPC 0100mmmm01001110 Privileged —...
Page 221 Table 7.8 System Control Instructions (cont) Instruction Operation Instruction Code Privileged T Bit SETS 0000000001011000 — — SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR,Rn 0000nnnn00000010 Privileged — GBR,Rn 0000nnnn00010010 — — VBR,Rn 0000nnnn00100010 Privileged — SSR,Rn 0000nnnn00110010 Privileged —...
Page 222: Table 7.9 Floating-Point Single-Precision Instructions
Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FLDI0 H'00000000 1111nnnn10001101 — — FLDI1 H'3F800000 1111nnnn10011101 — — FMOV FRm,FRn 1111nnnnmmmm1100 — — FMOV.S @Rm,FRn (Rm) 1111nnnnmmmm1000 — — FMOV.S @(R0,Rm),FRn (R0 + Rm) 1111nnnnmmmm0110 — —...
Page 223: Table 7.10 Floating-Point Double-Precision Instructions
Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — FFFF FADD DRm,DRn DRn + DRm 1111nnn0mmm00000 — — FCMP/EQ DRm,DRn When DRn = DRm, 1 1111nnn0mmm00100 — Comparison Otherwise, 0 result FCMP/GT...
Page 224: Table 7.12 Floating-Point Graphics Acceleration Instructions
Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit FMOV DRm,XDn 1111nnn1mmm01100 — — FMOV XDm,DRn 1111nnn0mmm11100 — — FMOV XDm,XDn 1111nnn1mmm11100 — — FMOV @Rm,XDn (Rm) 1111nnn1mmmm1000 — — FMOV @Rm+,XDn (Rm) XDn, Rm + 8 1111nnn1mmmm1001 —...
Page 225 Rev. 3.0, 04/02, page 186 of 1064...
Page 226: Section 8 Pipelining
Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7751 Series. Pipelines Figure 8.1 shows the basic pipelines.
Page 227: Figure 8.1 Basic Pipelines
1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction • Address •...
Page 228: Figure 8.2 Instruction Execution Patterns
1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.
Page 229 10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.
Page 230 19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.
Page 231 31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.
Page 232 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle : Cannot overlap a stage of the same kind, except when two instructions are Notes: executed in parallel.
Page 233: Parallel-Executability
Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.
Page 234 Table 8.1 Instruction Groups (cont) 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W...
Page 235 Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV...
Page 236 Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L...
Page 237: Execution Cycles And Pipeline Stalling
Table 8.2 Parallel-Executability 2nd Instruction Instruction O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: I-clock: CPU, FPU, MMU, caches B-clock: External bus controller P-clock: Peripheral units...
Page 238 The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 239 Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that attempts to use the locked resource is stalled (figure 8.3 (h)).
Page 240: Figure 8.3 Examples Of Pipelined Execution
(a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction. (b) Parallel execution: parallel-executable and no dependency 1 issue cycle EX-group ADD and LS-group MOV.L can...
Page 241 (e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result MOV.L @R1,R1 of ADD as its destination address.
Page 242 (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,FR1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency 11-cycle latency FSQRT FR4 FMOV FR0,FR4 10 stall cycles = latency (11) - 1 The registers are written-back in program order.
Page 243 (h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR GBR,R2 3 stall cycles FADD DR0,DR2 MAC.W @R1+,@R2+ 5 stall cycles...
Page 244: Table 8.3 Execution Cycles
Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Data transfer EXTS.B Rm,Rn — — — instructions EXTS.W Rm,Rn — — — EXTU.B Rm,Rn — — — EXTU.W Rm,Rn —...
Page 245 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Data transfer MOV.W R0,@(disp,Rn) — — — instructions MOV.L Rm,@(disp,Rn) — — — MOV.B Rm,@(R0,Rn) — — — MOV.W Rm,@(R0,Rn) —...
Page 246 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn — — — MAC.L @Rm+,@Rn+ 2/2/4/4...
Page 247 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — — — SHAD Rm,Rn —...
Page 248 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS — — — SETT —...
Page 249 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn — — — SPC,Rn —...
Page 250 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Single- FABS — — — precision FADD FRm,FRn — — — floating-point FCMP/EQ FRm,FRn — — — instructions FCMP/GT FRm,FRn —...
Page 251 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Double- FNEG — — — precision FSQRT (23, 24)/ floating-point instructions FSUB DRm,DRn (7, 8)/9 FTRC DRm,FPUL FPU system Rm,FPUL —...
Page 252 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6. FTRV latency “(L1, L2, L3, L4)/L5”: L1 is the latency for FR [n], L2 that for FR [n+1], L3 that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.
Page 253 Rev. 3.0, 04/02, page 214 of 1064...
Page 254: Section 9 Power-Down Modes
Section 9 Power-Down Modes Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: Sleep mode Deep sleep mode Standby mode...
Page 255: Table 9.1 Status Of Cpu And Peripheral Modules In Power-Down Modes
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status Power- On-chip Down Entering On-Chip Peripheral External Exiting Mode Conditions CPG Memory Modules Pins Memory Method Sleep SLEEP Operating Halted Held Operating Held Refresh- Interrupt instruction (registers Reset executed held) while STBY...
Page 256: Register Configuration
9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Area 7 Access Name Abbreviation Initial Value P4 Address Address Size Standby control STBCR H'00 H'FFC00004 H'1FC00004 register Standby control STBCR2 H'00 H'FFC00010 H'1FC00010 register 2 Clock stop register CLKSTP00...
Page 257: Register Descriptions
Register Descriptions 9.2.1 Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that specifies the power-down mode status. It is initialized to H'00 by a power-on reset via the pin or due to watchdog timer overflow. Bit: STBY MSTP4...
Page 258 Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again.
Page 259: Peripheral Module Pin High Impedance Control
Bit 0: MSTP0 Description SCI operates (Initial value) SCI clock supply is stopped 9.2.2 Peripheral Module Pin High Impedance Control When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go to the high-impedance state in standby mode. Relevant Pins SCI related pins MD0/SCK2...
Page 260: Standby Control Register 2 (Stbcr2)
9.2.4 Standby Control Register 2 (STBCR2) Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via pin or due to watchdog timer overflow. Bit: DSLP STHZ...
Page 261: Clock Stop Register 00 (Clkstp00)
Bit 0—Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller Stop Function for how to set the clock supply. Bit 0: MSTP5 Description UBC operating (Initial value)
Page 262: Clock Stop Clear Register 00 (Clkstpclr00)
Bit 1—Clock Stop 1 (CSTP1): Specifies stopping of the peripheral clock supply to timer unit (TMU) channels 3 and 4. Bit 1: CSTP1 Description Peripheral clock is supplied to TMU channels 3 and 4 (Initial value) Peripheral clock supply to TMU channels 3 and 4 is stopped Bit 0—Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt controller (INTC).
Page 263: Sleep Mode
Sleep Mode 9.3.1 Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Page 264: Exit From Deep Sleep Mode
Transition to Pin Sleep Mode Changing the pin to the low level causes the SH7751 Series to make a transition to sleep mode. To ensure that memory is correctly refreshed, use this function when the DSLP bit of STBCR2 is set to 0.
Page 265: Exit From Standby Mode
Table 9.4 State of Registers in Standby Mode Registers That Retain Module Initialized Registers Their Contents Interrupt controller — All registers User break controller — All registers Bus state controller — All registers On-chip oscillation circuits — All registers Timer unit TSTR register* All registers except TSTR Realtime clock...
Page 266: Clock Pause Function
Notes: *1 Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3– IRL0 level is higher than the SR register I3–I0 mask level). *2 GPIC can be used to cancel standby mode when the RTC clock (32.768 kHz) is operating (when the GPIC level is higher than the SR register I3–I0 mask level).
Page 267: Exit From Module Standby Function
Description CSTP2 Peripheral clock is supplied to PCIC Peripheral clock supply to PCIC is stopped CSTP1 Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supply to TMU channels 3 and 4 is stopped CSTP0 INTC detects PCIC and TMU channel 3 and 4 interrupts INTC does not detect PCIC and TMU channel 3 and 4 interrupts MSTP6 SQ operates...
Page 268: Hardware Standby Mode
Hardware Standby Mode 9.8.1 Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all modules other than the RTC stop, as in the standby mode selected using the SLEEP command. Hardware standby mode differs from standby mode as follows: 1.
Page 269: Usage Notes
9.8.3 Usage Notes The CA pin level must be kept high during the power-on oscillation settling period when the RTC power supply is started (figure 9.15). STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below. The meaning of the STATUS pin settings is as follows: Reset: HH (STATUS1 high, STATUS0 high)
Page 270: In Exit From Standby Mode
Manual Reset CKIO (High) Normal Reset Normal STATUS 0–30 Bcyc ≥ 0 Bcyc Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle. Figure 9.2 STATUS Output in Manual Reset 9.9.2 In Exit from Standby Mode...
Page 271: Figure 9.4 Status Output In Standby Power-On Reset Sequence
Standby Power-On Reset Oscillation stops Reset CKIO Normal Standby Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: *1 When standby mode is exited by means of a power-on reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time. *2 Undefined Figure 9.4 STATUS Output in Standby Power-On Reset Sequence...
Page 272: In Exit From Sleep Mode
Standby Manual Reset Oscillation stops Reset CKIO (High) Normal Standby Undefined Reset Normal STATUS 0–30 Bcyc 0–20 Bcyc Note: * When standby mode is exited by means of a manual reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time. Figure 9.5 STATUS Output in Standby Manual Reset Sequence 9.9.3...
Page 273: Figure 9.7 Status Output In Sleep Power-On Reset Sequence
Sleep Power-On Reset Reset CKIO Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: *1 When sleep mode is exited by means of a power-on reset, hold low for the oscillation stabilization time. *2 Undefined Figure 9.7 STATUS Output in Sleep Power-On Reset Sequence Rev.
Page 274: Figure 9.8 Status Output In Sleep Manual Reset Sequence
Sleep Manual Reset Reset CKIO (High) Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.8 STATUS Output in Sleep Manual Reset Sequence Rev. 3.0, 04/02, page 235 of 1064...
Page 275: In Exit From Deep Sleep Mode
9.9.4 In Exit from Deep Sleep Mode Deep Sleep Interrupt Interrupt request CKIO Sleep STATUS Normal Normal Figure 9.9 STATUS Output in Deep Sleep Interrupt Sequence Deep Sleep Power-On Reset Reset CKIO RESET * Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: *1 When deep sleep mode is exited by means of a power-on reset, hold RESET low for the oscillation stabilization time.
Page 276: Figure 9.11 Status Output In Deep Sleep Manual Reset Sequence
Deep Sleep Manual Reset Reset CKIO (High) Normal Reset Normal STATUS Sleep 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.11 STATUS Output in Deep Sleep Manual Reset Sequence Rev. 3.0, 04/02, page 237 of 1064...
Page 277: Hardware Standby Mode Timing
9.9.5 Hardware Standby Mode Timing Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode. After setting the pin level low, the clock starts when the CA pin level is switched to high. CKIO Normal Standby...
Page 278: Figure 9.13 Hardware Standby Mode Timing (When Ca = Low In Wdt Operation)
Interrupt request WDT overflow CKIO (High) Standby Normal Standby* STATUS 0–10 Bcyc WDT count Note: * High impedance when STBCR2. STHZ = 0 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) Min 0s Min 0s Max 50 µs Note: * V DD-CPG...
Page 279: Figure 9.15 Timing When Vdd-Rtc Power Is Off On
DD-RTC Power-on oscillation settling time Min 0s Note: * V DD-PLL1/2 DD-CPG Figure 9.15 Timing When VDD-RTC Power is Off Rev. 3.0, 04/02, page 240 of 1064...
Page 280: Section 10 Clock Oscillation Circuits
Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control. The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed.
Page 281 The WDT has the following features Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed. Can be switched between watchdog timer mode and interval timer mode Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow.
Page 282: Overview Of Cpg
10.2 Overview of CPG 10.2.1 Block Diagram of CPG Figures 10.1(1) and 10.1(2) show a block diagram of the CPG in the SH7751 and SH7751R. Oscillator circuit Frequency divider 2 × 1 PLL circuit 1 × 1/2 × 6 × 1/3 CPU clock (Iø)
Page 283: Figure 10.1(2) Block Diagram Of Cpg (Sh7751R)
Oscillator circuit Frequency divider 2 × 1 PLL circuit 1 × 1/2 × 6 × 1/3 × 12 CPU clock (Iø) × 1/4 cycle Icyc × 1/6 × 1/8 Crystal XTAL Peripheral module oscillator clock (Pø) cycle Pcyc EXTAL Bus clock (Bø) cycle Bcyc PLL circuit 2 ×...
Page 284 The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillator by 6 or 12. Starting and stopping is controlled by a frequency control register setting.
Page 285: Cpg Pin Configuration
10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Abbreviation Function Mode control pins Input Set clock operating mode Crystal I/O pins XTAL Output Connects crystal resonator (clock input pins) EXTAL Input Connects crystal resonator, or used as...
Page 286: Clock Operating Modes
Tables 10.3(1) and 10.3(2) show the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency division ratio). Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3(1) Clock Operating Modes (SH7751) External Frequency Pin Combination (vs.
Page 287: Table 10.4 Frqcr Settings And Internal Clock Frequencies
Table 10.4 FRQCR Settings and Internal Clock Frequencies Frequency Division Ratio FRQCR (Lower 9 Bits) CPU Clock Bus Clock Peripheral Module Clock 9'h000 9'h002 9'h004 9'h008 9'h00a 9'h00c 9'h011 9'h013 9'h01a 9'h01c 9'h023 9'h02c 9'h048 9'h04a 9'h04c 9'h05a 9'h05c 9'h063 9'h06c 9'h091 9'h093...
Page 288: Cpg Register Description
10.4 CPG Register Description 10.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be used on FRQCR.
Page 289 Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off. Bit 9: PLL2EN Description PLL circuit 2 is not used PLL circuit 2 is used (Initial value) Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency.
Page 290: Changing The Frequency
Bit 2: PFC2 Bit 1: PFC1 Bit 0: PFC0 Description Other than the above Setting prohibited (Do not set) 10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register.
Page 291: Changing Bus Clock Division Ratio (When Pll Circuit 2 Is On)
3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its up- count from the value set in step 1 above.
Page 292: Output Clock Control
10.6 Output Clock Control The CKIO pin can be switched between clock output and a high-impedance state by means of the CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is pulled up. 10.7 Overview of Watchdog Timer 10.7.1...
Page 293: Register Configuration
10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Initial Area 7 Name Abbreviation Value P4 Address Address Access Size Watchdog timer WTCNT R/W* H'00 H'FFC00008...
Page 294: Watchdog Timer Control/Status Register (Wtcsr)
10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the pin.
Page 295 Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF Description No overflow (Initial value) WTCNT has overflowed in watchdog timer mode Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in interval timer mode.
Page 296: Notes On Register Access
10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction.
Page 297: Using The Wdt
10.9 Using the WDT 10.9.1 Standby Clearing Procedure The WDT is used when clearing standby mode by means of an NMI or other interrupt. The procedure is shown below. (As the WDT does not operate when standby mode is cleared with a reset, the pin should be held low until the clock stabilizes.)
Page 298: Using Watchdog Timer Mode
10.9.3 Using Watchdog Timer Mode 1. Set the WT/ bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter. 2.
Page 299: Notes On Board Design
CL1 = CL2 = 0–33 pF R = 0Ω EXTAL XTAL SH7751 Series Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin.
Page 300: Figure 10.5 Points For Attention When Using Pll Oscillator Circuit
CPB1 = CPB2 = 10 µF RB = 10 Ω VSS-PLL1 CB = 10 µF RCB2 VDD-PLL2 1.8 V CPB2 SH7751 Series VSS-PLL2 VDD-CPG 3.3 V VSS-CPG Figure 10.5 Points for Attention when Using PLL Oscillator Circuit Rev. 3.0, 04/02, page 261 of 1064...
Page 301 Rev. 3.0, 04/02, page 262 of 1064...
Page 302: Section 11 Realtime Clock (Rtc)
Section 11 Realtime Clock (RTC) 11.1 Overview The SH7751 Series includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 11.1.1 Features The RTC has the following features. Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years.
Page 303: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. RTCCLK RESET, STBY, etc 16.384 kHz RTC crystal RTC operation 32.768 kHz Prescaler oscillator control unit 128 Hz RCR1 RCR2 Counter unit RCR3 Interrupt R64CNT control unit RSECCNT RMINCNT RHRCNT RDAYCNT...
Page 304: Pin Configuration
11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation Function RTC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillator RTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillator Clock input/clock output TCLK External clock input pin/input capture control input pin/RTC output pin...
Page 305 Table 11.2 RTC Registers (cont) Initialization Abbrevia- Power-On Manual Standby Initial Area 7 Access Name tion Reset Reset Mode Value P4 Address Address Size Month RMONCNT R/W Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8 counter Year RYRCNT R/W Counts Counts Counts Undefined H'FFC8001C H'1FC8001C 16...
Page 306: Register Descriptions
11.2 Register Descriptions 11.2.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.
Page 307: Minute Counter (Rmincnt)
11.2.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 308: Day-Of-Week Counter (Rwkcnt)
11.2.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 309: Day Counter (Rdaycnt)
11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 310: Year Counter (Ryrcnt)
Bit: — — — 10-month 1-month units unit Initial value: Undefined Undefined Undefined Undefined Undefined R/W: 11.2.8 Year Counter (RYRCNT) RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter.
Page 311: Second Alarm Register (Rsecar)
11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 312: Hour Alarm Register (Rhrar)
11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 313: Day Alarm Register (Rdayar)
Bit: — — — — Day-of-week code Initial value: Undefined Undefined Undefined R/W: Day-of-week code Day of week 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is compared with the RDAYCNT value.
Page 314: Month Alarm Register (Rmonar)
11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 315 Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again.
Page 316: Rtc Control Register 2 (Rcr2)
Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF Description Alarm registers and counter values do not match (Initial value)
Page 317 Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF Description Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF Interrupt is generated at interval specified by bits PES2–PES0...
Page 318 Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time.
Page 319: Rtc Control Register (Rcr3) And Year-Alarm Register (Ryrar)
11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) (SH7751R Only) RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC’s BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value.
Page 320: Operation
11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Set RCR2.RESET to 1 Stop clock Clear RCR2.START to 0 Reset frequency divider Set second/minute/hour/day/ In any order day-of-week/month/year Set RCR2.START to 1...
Page 321: Time Reading Procedures
The procedure for setting the time while the clock is running is shown in figure 11.2 (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data.
Page 322: Figure 11.3 Examples Of Time Reading Procedures
Clear RCR1.CIE to 0 Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag is not cleared) Read counter register Carry flag = 1? Read RCR1 register and check CF bit (a) Reading time without using interrupts Clear carry flag Set RCR1.CIE to 1 Enable carry interrupts...
Page 323: Alarm Function
11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Be sure to reset the flag as it may have been Clear alarm flag set during alarm time setting Set RCR1.AIE to 1 Enable alarm interrupts...
Page 324: Interrupts
11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2–...
Page 325: Figure 11.5 Example Of Crystal Oscillator Circuit Connection
SH7751 Series EXTAL2 XTAL2 VDD-RTC VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value R (typ.
Page 326: Section 12 Timer Unit (Tmu)
Section 12 Timer Unit (TMU) 12.1 Overview The SH7751 Series includes an on-chip 32-bit timer unit (TMU) comprising five 32-bit timer channels (channels 0 to 4). 12.1.1 Features The TMU has the following features. Auto-reload type 32-bit down-counter provided for each channel...
Page 327: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. TICPI2 RESET, STBY, TUNI0,1 PCLK/4, 16, 64* TUNI2 TCLK RTCCLK TUNI3, TUNI4 etc. TCLK Prescaler operation control unit control unit To chan- To chan- TOCR nels nels 0 to 4 0 to 2 TSTR TSTR2...
Page 328: Register Configuration
12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Com- Timer TOCR R/W Ini- Ini- Held H'00 H’FFD80000 H'1FD80000 8...
Page 329: Register Descriptions
Table 12.2 TMU Registers (cont) Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Timer TCOR3 R/W Ini- Held Held H'FFFFFFFF H'FE100008 H'1E100008 32 constant tialized register 3 Timer TCNT3 R/W Ini- Held...
Page 330: Timer Start Register (Tstr)
Bit 0—Timer Clock Pin Control (TCOE): Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin. Bit 0: TCOE Description Timer clock pin (TCLK) is used as external clock input or input capture control input pin (Initial value) Timer clock pin (TCLK) is used as on-chip RTC output clock output pin*...
Page 331: Timer Start Register 2 (Tstr2)
Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or stopped. Bit 1: STR1 Description TCNT1 count operation is stopped (Initial value) TCNT1 performs count operation Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or stopped.
Page 332: Timer Constant Registers (Tcor)
Bit 0—Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) is operated or stopped. Bit 0: STR3 Description TCNT3 count operation is stopped (Initial value) TCNT3 performs count operation 12.2.4 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are five TCOR registers, one for each channel.
Page 333: Timer Control Registers (Tcr)
The TCNT registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents by a manual reset or in standby mode. Bit: · · · · · · · · · · · · · Initial value: R/W: In channels 0 to 2, when the input clock is the on-chip RTC output clock (RTCCLK), TCNT...
Page 334 2. Channel 2 TCR bit configuration Bit: — — — — — — ICPF Initial value: R/W: Bit: ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: R/W: 3. Channel 3 and 4 TCR bit configuration Bit: — — —...
Page 335 Bit 8—Underflow Flag (UNF): Status flag that indicates the occurrence of underflow. Bit 8: UNF Description TCNT has not underflowed (Initial value) [Clearing condition] When 0 is written to UNF TCNT has underflowed [Setting condition] When TCNT underflows* Note: * Writing 1 does not change the value. Bits 7 and 6—Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used.
Page 336: Input Capture Register (Tcpr2)
Bit 5: UNIE Description Interrupt due to underflow (TUNI) is not enabled (Initial value) Interrupt due to underflow (TUNI) is enabled Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): In channels 0 to 2, these bits select the external clock input edge when an external clock is selected or the input capture function is used.
Page 337: Operation
TCPR2 is not initialized by a power-on or manual reset, or in standby mode. Bit: · · · · · · · · · · · · · Initial value: Undefined R/W: 12.3 Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32- bit timer constant register (TCOR).
Page 338: Figure 12.2 Example Of Count Operation Setting Procedure
Operation selection Select count clock Underflow interrupt generation setting When input capture function is used Input capture interrupt generation setting Timer constant register setting Set initial timer counter value Start count Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated.
Page 339: Figure 12.4 Count Timing When Operating On Internal Clock
TCNT Count Timing: Operating on internal clock Any of five count clocks (P /4, P /16, P /64, P /256, or P /1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0 bits in TCR. Figure 12.4 shows the timing in this case.
Page 340: Input Capture Function
RTC output clock N + 1 N – 1 TCNT Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock 12.3.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1.
Page 341: Interrupts
TCOR value set in TCNT TCNT value on underflow TCOR H'00000000 Time TCLK TCNT value set TCPR2 TICPI2 Figure 12.7 Operation Timing when Using Input Capture Function 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used).
Page 342: Usage Notes
Table 12.3 TMU Interrupt Sources Channel Interrupt Source Description TUNI0 Underflow interrupt 0 TUNI1 Underflow interrupt 1 TUNI2 Underflow interrupt 2 TICPI2 Input capture interrupt 2 TUNI3 Underflow interrupt 3 TUNI4 Underflow interrupt 4 12.5 Usage Notes 12.5.1 Register Writes When performing a TMU register write, timer count operation must be stopped by clearing the start bit (STR0–STR4) for the relevant channel in the timer start register (TSTR, TSTR2).
Page 343 Rev. 3.0, 04/02, page 304 of 1064...
Page 344: Section 13 Bus State Controller (Bsc)
The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be connected to the SH7751 Series and also support the PCMCIA interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system.
Page 345 Consecutive accesses to the same row address Connectable area: 3 Settable bus widths: 32, 16 Synchronous DRAM interface Row address/column address multiplexing according to synchronous DRAM capacity Burst operation Auto-refresh and self-refresh Synchronous DRAM control signal timing can be controlled by register settings Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 32...
Page 346: Block Diagram
13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. interface WCR1 Wait control unit WCR2 WCR3 BCR1 – Area control unit – BCR2 BCR3 * BCR4 * – Memory control unit RFCR RTCNT Refresh Interrupt Comparator control unit controller RTCOR RTCSR...
Page 347: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Signals Description Address bus A25–A0 Address output Data bus D31–D0 Data input/output Bus cycle start Signal that indicates the start of a bus cycle When setting synchronous DRAM interface or MPX interface: asserted once for a burst transfer For other burst transfers: asserted each data cycle Chip select 6–0...
Page 348 Table 13.1 BSC Pins (cont) Name Signals Description Column address /DQM0 When setting DRAM interface: signal for strobe 0 D7–D0 When setting synchronous DRAM interface: selection signal for D7–D0 Column address /DQM1 When setting DRAM interface: signal for strobe 1 D15–D8 When setting synchronous DRAM interface:...
Page 349: Register Configuration
The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as an SH7751 Series register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing.
Page 350: Overview Of Areas
(MMU). Details are given in section 3, Memory Management Unit (MMU). This section describes the areas into which the external address is divided. With the SH7751 Series, various kinds of memory or PC cards can be connected to the seven areas of external address as shown in table 13.3, and chip select signals (...
Page 351: Table 13.3 External Memory Space Map
Table 13.3 External Memory Space Map External Connectable Settable Bus Area Addresses Size Memory Widths Access Size H'00000000– 64 Mbytes SRAM 8, 16, 32* 8, 16, 32, H'03FFFFFF bits, Burst ROM 8, 16, 32* 32 bytes H'04000000– 64 Mbytes SRAM 8, 16, 32* 8, 16, 32, H'07FFFFFF...
Page 352: Figure 13.3 External Memory Space Allocation
Figure 13.3 External Memory Space Allocation Memory Bus Width: In the SH7751 Series, the memory bus width can be set independently for each space. For area 0, a bus size of 8, 16, or 32 bits can be selected in a power-on reset by means...
Page 353: Pcmcia Support
The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used. 13.1.6 PCMCIA Support The SH7751 Series supports PCMCIA interface specifications for external memory space areas 5 and 6. The interfaces supported are the IC memory card interface and I/O card interface stipulated in JEIDA specifications version 4.2 (PCMCIA2.1).
Page 354: Table 13.5 Pcmcia Support Interfaces
Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7751 Series Name I/O Function Name I/O Function Ground Ground — I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data...
Page 355 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7751 Series Name I/O Function Name I/O Function Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data ...
Page 356 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7751 Series Name I/O Function Name I/O Function Reserved Reserved — RESET Reset RESET Reset Output from port Wait request Wait request...
Page 357: Register Descriptions
13.2 Register Descriptions 13.2.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 358 Bit 31: ENDIAN Description In a power-on reset, the endian setting external pin (MD5) is low, designating big-endian mode for the SH7751 Series In a power-on reset, the endian setting external pin (MD5) is high, designating little-endian mode for the SH7751 Series Bit 30—Master/Slave Flag (MASTER): Samples the value of the master/slave specification...
Page 359 Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor status for control input pins (NMI, – , MD6/ ). IPUP is initialized by a power-on reset. Bit 25: IPUP Description Pull-up resistor is on for control input pins (NMI, –...
Page 360 Bit 19—BREQ Enable (BREQEN): Indicates whether external requests and bus requests from PCIC can be accepted. BREQEN is initialized to the external request and bus request from PCIC acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup. The bus request from the PCIC is always accepted in a slave mode start up.
Page 361 Bit 14—High Impedance Control (HIZCNT): Specifies the state of the signals in standby mode and when the bus is released. Bit 14: HIZCNT Description /DQMn, and signals go to high- impedance (Hi-Z) in standby mode and when the bus is released (Initial value) ...
Page 362 Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0...
Page 363 Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 Bit 6: A6BST1 Bit 5: A6BST0...
Page 364 Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be directly connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description Areas 2 and 3 are accessed as SRAM interface or MPX interface*...
Page 365: Bus Control Register 2 (Bcr2)
13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 32-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 366: Bus Control Register 3 (Bcr3) (Sh7751R Only)
Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify the bus width of area n (n = 1 to 6). (Bit 0): PORTEN Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Description Reserved (Setting prohibited) Bus width is 8 bits Bus width is 16 bits...
Page 367 Bit: Bit name: A1MPX A4MPX — — — — — MEMMODE Initial value: R/W: Bit: Bit name: — — — — — — — SDBL Initial value: R/W: Bit 15 A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by MEMMPX.
Page 368: Bus Control Register 4 (Bcr4) (Sh7751R Only)
13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only) Bus control register 4 (BCR4) is a register that enables asynchronous input for pins corresponding to individual bits. The BCR4 register is a 32-bit readable/writable register. It is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 369 Bits 4 to 0—Asynchronous Input: These bits enable asynchronous input for the corresponding pins. Bit 4–0: ASYNCn Description Corresponding pin is synchronous input with respect to CKIO (Initial value) Asynchronous input with respect to CKIO is enabled for corresponding pin ...
Page 370: Wait Control Register 1 (Wcr1)
In the SH7751 Series, the number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision.
Page 371 same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual address transfer, inter-area idle cycles are inserted. Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the same space.
Page 372: Table 13.6 Idle Insertion Between Accesses
Table 13.6 Idle Insertion between Accesses Following Cycle Same Different Same Area Different Area Area Area Read Write Read Write Preceding Address Address Cycle CPU DMA CPU DMA CPU DMA CPU DMA Output Output Read M (1) M (1) Write DMA read —...
Page 373: Wait Control Register 2 (Wcr2)
13.2.6 Wait Control Register 2 (WCR2) Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of wait states to be inserted for each area. It also specifies the data access pitch when performing burst memory access. This enables low-speed memory to be connected without using external circuitry.
Page 374 Bits 31 to 29—Area 6 Wait Control (A6W2–A6W0): These bits specify the number of wait states to be inserted for area 6. For the case where an MPX interface setting is made, see table 13.7. Description First Cycle Bit 31: A6W2 Bit 30: A6W1 Bit 29: A6W0 Inserted Wait States...
Page 375 Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait states to be inserted for area 5. For the case where an MPX interface setting is made, see table 13.7. Description First Cycle Bit 25: A5W2 Bit 24: A5W1 Bit 23: A5W0 Inserted Wait States...
Page 376 Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait states to be inserted for area 4. For the case where an MPX interface setting is made, see table 13.7. Description Bit 19: A4W2 Bit 18: A4W1 Bit 17: A4W0 Inserted Wait States Ignored...
Page 377 When DRAM or Synchronous DRAM Interface is Set* Note: * External wait input is always ignored Description DRAM Synchronous DRAM Bit 15: A3W2 Bit 14: A3W1 Bit 13: A3W0 Assertion Width Latency Cycles Inhibited Inhibited Inhibited Note: * Inhibited in RAS down mode Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states to be inserted for area 2.
Page 378 When Synchronous DRAM Interface is Set * Description Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0 Synchronous DRAM Latency Cycles Inhibited Inhibited Inhibited Notes: *1 External wait input is always ignored *2 Inhibited in RAS down mode Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states to be inserted for area 1.
Page 379 Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait states to be inserted for area 0. For the case where an MPX interface setting is made, see table 13.7. Description First Cycle Bit 5: A0W2 Bit 4: A0W1 Bit 3: A0W0...
Page 380: Table 13.7 When Mpx Interface Is Set (Areas 0 To 6)
Table 13.7 When MPX Interface is Set (Areas 0 to 6) Description Inserted Wait States 1st Data 2nd Data AnW2 AnW1 AnW0 Read Write Onward Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled (n = 6 to 0) Rev. 3.0, 04/02, page 341 of 1064...
Page 381: Wait Control Register 3 (Wcr3)
R/W* Note: * These bits can be set only in the SH7751R. Bits 31 to 27, 23, 19*, 15, 11, 7*, and 3 (SH7751) Bits 31 to 27, 23, 15, 11, and 3 (SH7751R) Reserved: These bits are always read as 0, and should only be written with 0.
Page 382 Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface: Bit 4n + 2: AnS0 Waits Inserted in Setup (Initial value)
Page 383: Memory Control Register (Mcr)
13.2.8 Memory Control Register (MCR) The memory control register (MCR) is a 32-bit readable/writable register that specifies timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected without using external circuitry.
Page 384 Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS down mode is used, set BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both designated as synchronous DRAM interface. Bit 31: RASD Description Normal mode...
Page 385 Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is set, these bits specify the minimum number of cycles until is asserted again after being negated. When the synchronous DRAM interface is set, these bits specify the minimum number of cycles until the next bank active command is output after precharging.
Page 386 Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0 Write Precharge ACT Delay Time 1 (Initial value) Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Note: * Inhibited in RAS down mode Bits 12 to 10—CAS-Before-RAS Refresh Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the assertion period in CAS-before-RAS refreshing.
Page 387 EDOMODE 8/16/32/64-Bit Transfer 32-Byte Transfer Single Single Setting prohibited Setting prohibited Single/fast page* Fast page Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM.
Page 388 For Synchronous DRAM Interface: Example Synchronous DRAM AMXEXT Configurations BANK (16M: 512k 16 bits a[21]* (16M: 512k 16 bits a[20]* (16M: 1M 8 bits a[22]* (16M: 1M 8 bits a[21]* — (64M: 1M 16 bits a[23:22]* — (64M: 2M 8 bits a[24:23]* —...
Page 389: Pcmcia Control Register (Pcr)
Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of memory other than DRAM. Set this bit to 1 only when DRAM is used. 13.2.9 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the...
Page 390 Bit 13: A6PCW1 Bit 12: A6PCW0 Waits Inserted 0 (Initial value) Bits 11 to 9—Address-OE/WE Assertion Delay (A5TED2–A5TED0): These bits set the delay time from address output to assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Bit 11: A5TED2 Bit 10: A5TED1 Bit 9: A5TED0...
Page 391: Synchronous Dram Mode Register (Sdmr)
Bit 5: A5TEH2 Bit 4: A5TEH1 Bit 3: A5TEH0 Waits Inserted 0 (Initial value) Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address hold delay time from negation in a write on the connected PCMCIA interface or in an I/O card read.
Page 392 DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of the SH7751 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7751 Series, the value actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right.
Page 393: Refresh Timer Control/Status Register (Rtcsr)
For a 32-bit bus: Address WT BL2 BL1 BL0 10 bits set in case of 32-bit bus width LMODE: RAS-CAS latency Burst length Wrap type (0: Sequential) LMODE 000: Reserved 000: Reserved 001: Reserved 001: 1 010: 4 010: 2 011: 8* 011: 3 100: Reserved...
Page 394 Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.15, Notes on Accessing Refresh Control Registers. Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values. Bit 7: CMF Description RTCNT and RTCOR values do not match...
Page 395: Refresh Timer Counter (Rtcnt)
Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified by the LMTS bit in RTCSR. Bit 2: OVF Description RFCR has not overflowed the count limit indicated by LMTS (Initial value) [Clearing condition] When 0 is written to OVF...
Page 396: Refresh Time Constant Register (Rtcor)
Bit: — — — — — — — — Initial value: R/W: — — — — — — — — Bit: Initial value: R/W: 13.2.13 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper limit of the RTCNT counter.
Page 397: Refresh Count Register (Rfcr)
13.2.14 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of refreshes by being incremented each time the RTCOR register and RTCNT counter values match. If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR register, the OVF flag is set in the RTCSR register and the RFCR register is cleared.
Page 398: Operation
13.3.1 Endian/Access Size and Data Alignment The SH7751 Series supports both big-endian mode, in which the most significant byte (MSByte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (LSByte) is at the 0 address end.
Page 399: Table 13.8 32-Bit External Device/Big-Endian Access And Data Alignment
Data Configuration Byte Data 7–0 Word Data 15–8 Data 7–0 Longword Data 31–24 Data 23–16 Data 15–8 Data 7–0 Quadword Data Data Data Data Data Data Data Data 63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0 Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals...
Page 400: Table 13.9 16-Bit External Device/Big-Endian Access And Data Alignment
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte — — Data — Asserted 7–0 2n+1 —...
Page 401: Table 13.10 8-Bit External Device/Big-Endian Access And Data Alignment
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte — — — Data Asserted 7–0 Word —...
Page 402: Table 13.11 32-Bit External Device/Little-Endian Access And Data Alignment
Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte — — Data Asserted 7–0 4n+1 —...
Page 403: Table 13.12 16-Bit External Device/Little-Endian Access And Data Alignment
Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte — — — Data Asserted 7–0 2n+1 —...
Page 404: Table 13.13 8-Bit External Device/Little-Endian Access And Data Alignment
Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte — — — Data Asserted 7–0 Word —...
Page 405: Areas
13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set for this area. A bus width of 8, 16, or 32 bits can be selected in a power-on reset by means of external pins MD4 and MD3.
Page 406 Area 2: For area 2, external address bits A28 to A26 are 010. SRAM, MPX, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A2SZ1 and A2SZ0 in the BCR2 register.
Page 407 The read/write strobe signal address and setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3 register. When synchronous DRAM interface is set, the signals, RD/ signal, and byte control signals DQM0 to DQM3 are asserted, and address multiplexing is performed.
Page 408 , and the , and signals, which can be used as , and , respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( When the burst function is used, the number of burst cycle transfer states is determined in the range 2 to 9 according to the number of waits.
Page 409: Sram Interface
13.3.3 SRAM Interface Basic Timing: The SRAM interface of the SH7751 Series uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the SRAM timing of normal space accesses. A no-wait normal access is completed in two cycles. The signal is asserted for one cycle to indicate the start of a bus cycle.
Page 410: Figure 13.6 Basic Timing Of Sram Interface
CKIO A25–A0 D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Single address DMA Dual address DMA Figure 13.6 Basic Timing of SRAM Interface Rev. 3.0, 04/02, page 371 of 1064...
Page 411: Figure 13.7 Example Of 32-Bit Data Width Sram Connection
Figures 13.7, 13.8, and 13.9 show examples of connection to 32-, 16-, and 8-bit data width SRAM. 128k × 8-bit SH7751 Series SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 13.7 Example of 32-Bit Data Width SRAM Connection...
Page 412: Figure 13.8 Example Of 16-Bit Data Width Sram Connection
128k × 8-bit SH7751 Series SRAM I/O7 I/O0 I/O7 I/O0 Figure 13.8 Example of 16-Bit Data Width SRAM Connection Rev. 3.0, 04/02, page 373 of 1064...
Page 413: Figure 13.9 Example Of 8-Bit Data Width Sram Connection
128k × 8-bit SH7751 Series SRAM I/O7 I/O0 Figure 13.9 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification.
Page 414: Figure 13.10 Sram Interface Wait Timing (Software Wait Only)
CKIO A25–A0 D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.10 SRAM Interface Wait Timing (Software Wait Only) Rev.
Page 415: Figure 13.11 Sram Interface Wait State Timing (Wait State Insertion By Signal)
When software wait insertion is specified by WCR2, the external wait input signal is also sampled. signal sampling is shown in figure 13.11. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, signal has no effect if asserted in the T1 cycle or the first Tw cycle.
Page 416: Figure 13.12 Sram Interface Wait State Timing (Read Strobe Negate Timing Setting)
Read-Strobe Negate Timing (Setting Only Possible in the SH7751R): When the SRAM interface is used, timing for the negation of the strobe during read operations can be specified by the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this setting, see the description of the WCR3 register.
Page 417: Dram Interface
Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to 100, area 3 becomes DRAM interface. The DRAM interface function can then be used to connect DRAM to the SH7751 Series. 16 or 32 bits can be selected as the interface data width.
Page 418: Table 13.14 Relationship Between Amxext And Amx2-0 Bits And Address Multiplexing
DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to the SH7751 Series without using an external address multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting bits AMXEXT and AMX2–0 in MCR.
Page 419: Figure 13.14 Basic Dram Access Timing
Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.14. Tpc is the precharge cycle, Tr the assert cycle, Tc1 the assert cycle, and Tc2 the read data latch cycle. CKIO Address Column D31–D0...
Page 420: Figure 13.15 Dram Wait State Timing
Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.15.
Page 421: Figure 13.16 Dram Burst Access Timing
Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access.
Page 422: Figure 13.17 Dram Bus Cycle (Edo Mode, Rcd = 0, Anw = 0, Tpc = 1)
In the SH7751 Series, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM.
Page 423: Figure 13.18 Burst Access Timing In Dram Edo Mode
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.18 Burst Access Timing in DRAM EDO Mode RAS Down Mode: The SH7751 Series has an address comparator for detecting row address matches in burst mode. By using this address comparator, and also setting RAS down mode...
Page 424: Figure 13.19(1) Dram Burst Bus Cycle, Ras Down Mode Start (Fast Page Mode, Rcd = 0, Anw = 0)
CKIO Address D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) Rev.
Page 425: Figure 13.19(2) Dram Burst Bus Cycle, Ras Down Mode Continuation (Fast Page Mode, Rcd = 0, Anw = 0)
Tnop CKIO Address End of RAS down mode D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) Rev.
Page 426: Figure 13.19(3) Dram Burst Bus Cycle, Ras Down Mode Start (Edo Mode, Rcd = 0, Anw = 0)
CKIO Address D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) Rev.
Page 427: Figure 13.19(4) Dram Burst Bus Cycle, Ras Down Mode Continuation (Edo Mode, Rcd = 0, Anw = 0)
Tnop CKIO Address End of RAS down mode D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) Rev.
Page 428: Figure 13.20 Cas-Before-Ras Refresh Operation
refresh request is generated and the pin goes high. If the SH7751 Series external bus can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 13.20 shows the operation of CAS-before-RAS refreshing.
Page 429: Figure 13.21 Dram Cas-Before-Ras Refresh Cycle Timing (Tras = 0, Trc = 1)
Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) Self-Refresh The self-refreshing supported by the SH7751 Series is shown in figure 13.22. After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately after the end of the self-refreshing can be set by bits TRC2–TRC0 in MCR.
Page 430 Therefore, normal refreshing can be performed by having the pin monitored by a bus master other than the SH7751 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7751 Series. Rev. 3.0, 04/02, page 391 of 1064...
Page 431: Figure 13.22 Dram Self-Refresh Cycle Timing
TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 D63–D0 Figure 13.22 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 s or 200 s) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles.
Page 432: Synchronous Dram Interface
DRAM interface; if set to 011, areas 2 and 3 are both synchronous DRAM interface. The SH7751 Series supports burst read and burst write operations with a burst length of 4 as a synchronous DRAM operating mode. The data bus width is 32 bit, and the SZ size bits in MCR must be set to 11.
Page 433: Figure 13.23 Example Of 32-Bit Data Width Synchronous Dram Connection (Area 3)
When A0, the LSB of the synchronous DRAM address, is connected to the SH7751 Series, it makes a longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of the SH7751 Series, then connect pin A1 to pin A3.
Page 434: Table 13.15 Example Of Correspondence Between Sh7751 Series And Synchronous Dram
READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle. In the SH7751 Series, the number of Tpc cycles is determined by the specification of bits TPC2–TPC0 in MCR, and commands are not issued for the synchronous DRAM during this interval.
Page 435: Figure 13.24 Basic Timing For Synchronous Dram Burst Read
Figure 13.24 Basic Timing for Synchronous DRAM Burst Read Rev. 3.0, 04/02, page 396 of 1064...
Page 436 READA command reads the 16 bytes of data, which is the remainder of the data between 32-byte boundaries. Single Read: With the SH7751 Series, as synchronous DRAM is set to burst read/burst write mode, read data output continues after the required data has been read. To prevent data collisions, after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the SH7751 Series waits for the end of the synchronous DRAM operation.
Page 437: Figure 13.25 Basic Timing For Synchronous Dram Single Read
Figure 13.25 Basic Timing for Synchronous DRAM Single Read Burst Write: The timing chart for a burst write is shown in figure 13.26. In the SH7751 Series, a burst write occurs only in the event of 32-byte transfer. In a burst write operation, the WRIT command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output and, 4 cycles later, the WRITA command is issued.
Page 438: Figure 13.26 Basic Timing For Synchronous Dram Burst Write
Figure 13.26 Basic Timing for Synchronous DRAM Burst Write Rev. 3.0, 04/02, page 399 of 1064...
Page 439 The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is asserted two cycles before the data write cycle. The SH7751 Series supports burst-length 4 burst read and burst write operations of synchronous DRAM. A wait cycle is therefore generated even with single write operations.
Page 440: Figure 13.27 Basic Timing For Synchronous Dram Single Write
Trw1 Trw1 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D31–D0 (write) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.27 Basic Timing for Synchronous DRAM Single Write Rev.
Page 441 RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
Page 442: Figure 13.28 Burst Read Timing
Figure 13.28 Burst Read Timing Rev. 3.0, 04/02, page 403 of 1064...
Page 443: Figure 13.29 Burst Read Timing (Ras Down, Same Row Address)
Tc3 Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.29 Burst Read Timing (RAS Down, Same Row Address) Rev.
Page 444: Figure 13.30 Burst Read Timing (Ras Down, Different Row Addresses)
Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses) Rev. 3.0, 04/02, page 405 of 1064...
Page 445: Figure 13.31 Burst Write Timing
Figure 13.31 Burst Write Timing Rev. 3.0, 04/02, page 406 of 1064...
Page 446: Figure 13.32 Burst Write Timing (Same Row Address)
Figure 13.32 Burst Write Timing (Same Row Address) Rev. 3.0, 04/02, page 407 of 1064...
Page 447: Figure 13.33 Burst Write Timing (Different Row Addresses)
Figure 13.33 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM.
Page 448: Table 13.16 Cycles In Which Pipelined Access Can Be Used
possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch cycle, or during the data write cycle, and so shorten the access cycle. When a read access is followed by another read access to the same row address, after a READ command has been issued, another READ command is issued before the end of the data latch cycle, so that there is read data on the data bus continuously.
Page 449: Figure 13.34 Burst Read Cycle For Different Bank And Row Address Following Preceding Burst Read Cycle
Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Rev. 3.0, 04/02, page 410 of 1064...
Page 450: Figure 13.35 Auto-Refresh Operation
Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
Page 451: Figure 13.36 Synchronous Dram Auto-Refresh Timing
RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7751 Series standby function, and is maintained even after recovery from standby mode other than through a power-on reset.
Page 452: Figure 13.37 Synchronous Dram Self-Refresh Timing
Therefore, normal refreshing can be performed by having the pin monitored by a bus master other than the SH7751 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7751 Series. Rev. 3.0, 04/02, page 413 of 1064...
Page 453 To set burst read/burst write, CAS latency 1 to 3, wrap type = sequential, and burst length 4, 8*, supported by the SH7751 Series, arbitrary data is written by byte-size access to the following addresses.
Page 454: Figure 13.38(1) Synchronous Dram Mode Write Timing (Pall)
Synchronous DRAM mode register setting should be executed once only after power-on reset and before synchronous DRAM access, and no subsequent changes should be made. TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address D31–D0 (High) Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL) Rev.
Page 455: Figure 13.38(2) Synchronous Dram Mode Write Timing (Mode Register Setting)
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address D31–D0 (High) Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) Changing the Burst Length (SH7751R Only): When synchronous DRAM is connected with the 32-bit memory bus of the SH7751R, a burst length of either 4 or 8 can be selected by the setting of the SDBL bit of the BCR3 register.
Page 456: Figure 13.39 Basic Timing Of A Burst Read From Synchronous Dram (Burst Length = 8)
by the setting of the TPC2 to TPC0 bits of the MCR, and no command that operates on the synchronous DRAM is issued during these cycles. Figure 13.39 shows an example of the basic timing of a burst-read. To allow the connection of a lower-speed DRAM, the cycle’s period can be extended by the settings of the bits in WCR2 and MCR.
Page 457: Figure 13.40 Basic Timing Of A Burst Write To Synchronous Dram
In a cycle of access to synchronous DRAM, the signal is asserted for one clock cycle at the beginning of a bus cycle. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between the 32-bit boundaries that include the missed data are first read; after that, the data between 32-byte boundaries that include the missed data are read in a wraparound way.
Page 458: Burst Rom Interface
13.3.6 Burst ROM Interface Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a non- zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 13.41.
Page 459: Figure 13.41 Burst Rom Basic Access Timing
CKIO A25–A5 A4–A0 D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.41 Burst ROM Basic Access Timing Rev. 3.0, 04/02, page 420 of 1064...
Page 460: Figure 13.42 Burst Rom Wait Access Timing
CKIO A25–A5 A4–A0 D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.42 Burst ROM Wait Access Timing CKIO A25–A5 A4–A0 D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 461: Pcmcia Interface
13.3.7 PCMCIA Interface In the SH7751 Series, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1).
Page 462 insertion specified by WCR2. AnTED2–AnTED0 can be set to a value from 0 to 15, enabling the address, , and setup times with respect to the signals to be secured. AnTEH2–AnTEH0 can also be set to a value from 0 to 15, enabling the address, , and...
Page 463: Table 13.17 Relationship Between Address And Ce When Using Pcmcia Interface
Table 13.17 Relationship between Address and CE When Using PCMCIA Interface Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Read Even Don’t — Invalid Read data care Don’t — Invalid Read data care Even Don’t...
Page 464 Table 13.17 Relationship between Address and CE When Using PCMCIA Interface (cont) Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Dynamic Read Even — Invalid Read data — Read data Invalid sizing* Even —...
Page 465: Figure 13.44 Example Of Pcmcia Interface
A25–A0 A25–A0 D15–D0 D7–D0 D15–D0 PC card D15–D8 (memory I/O) SH7751 Series Card detection CD1, CD2 circuit A25–A0 D7–D0 D15–D0 D15–D8 PC card (memory I/O) Card CD1, CD2 detection circuit Figure 13.44 Example of PCMCIA Interface Rev. 3.0, 04/02, page 426 of 1064...
Page 466: Figure 13.45 Basic Timing For Pcmcia Memory Card Interface
Memory Card Interface Basic Timing: Figure 13.45 shows the basic timing for the PCMCIA memory card interface, and figure 13.46 shows the wait timing for the PCMCIA memory card interface. Tpcm1 Tpcm2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 467: Figure 13.46 Wait Timing For Pcmcia Memory Card Interface
Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.46 Wait Timing for PCMCIA Memory Card Interface Rev.
Page 468: Figure 13.47 Pcmcia Space Allocation
Common memory (64 MB) Virtual Access address space by CS5 wait External I/O controller addresses 1 kB IO 1 Virtual Access page address space by CS6 wait IO 1 controller Common IO 2 memory 1 Common Card 1 memory 2 on CS5 IO 2 Attribute memory...
Page 469: Figure 13.48 Basic Timing For Pcmcia I/O Card Interface
Tpci1 Tpci2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.48 Basic Timing for PCMCIA I/O Card Interface Rev. 3.0, 04/02, page 430 of 1064...
Page 470: Figure 13.49 Wait Timing For Pcmcia I/O Card Interface
Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.49 Wait Timing for PCMCIA I/O Card Interface Rev.
Page 471: Figure 13.50 Dynamic Bus Sizing Timing For Pcmcia I/O Card Interface
Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w CKIO A25–A1 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.
Page 472: Mpx Interface
13.3.8 MPX Interface If the MD6 pin is cleared to 0 in a power-on reset by means of the pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1 and MEMMODE, A4MPX, and A1MPX in BCR3.
Page 473: Figure 13.51 Example Of 32-Bit Data Width Mpx Connection
MPX device SH7751 Series CKIO D31–D0 I/O31–I/O0 Figure 13.51 Example of 32-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 bit should be specified in BCR2.
Page 474: Figure 13.52 Mpx Interface Timing 1 (Single Read Cycle, Anw = 0, No External Wait)
Tmd1w Tmd1 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 435 of 1064...
Page 475: Figure 13.53 Mpx Interface Timing 2 (Single Read, Anw = 0, One External Wait Inserted)
Tmd1w Tmd1w Tmd1 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted) Rev. 3.0, 04/02, page 436 of 1064...
Page 476: Figure 13.54 Mpx Interface Timing 3 (Single Write Cycle, Anw = 0, No External Wait)
Tmd1 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 437 of 1064...
Page 477: Figure 13.55 Mpx Interface Timing 4 (Single Write, Anw = 1, One External Wait Inserted)
Tmd1w Tmd1w Tmd1 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted) Rev. 3.0, 04/02, page 438 of 1064...
Page 478: Figure 13.56 Mpx Interface Timing 5 (Burst Read Cycle, Anw = 0, No External Wait)
Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 439 of 1064...
Page 479: Figure 13.57 Mpx Interface Timing 6 (Burst Read Cycle, Anw = 0, External Wait Control)
Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control) Rev. 3.0, 04/02, page 440 of 1064...
Page 480: Figure 13.58 Mpx Interface Timing 7 (Burst Write Cycle, Anw = 0, No External Wait)
Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 441 of 1064...
Page 481: Figure 13.59 Mpx Interface Timing 8 (Burst Write Cycle, Anw = 1, External Wait Control)
Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control) Rev. 3.0, 04/02, page 442 of 1064...
Page 482: Figure 13.60 Mpx Interface Timing 1 (Burst Read Cycle, Anw = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.60 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.
Page 483 Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.61 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.
Page 484: Figure 13.62 Mpx Interface Timing
Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.62 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.
Page 485: Figure 13.63 Mpx Interface Timing
Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.63 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.
Page 486: Figure 13.64 Mpx Interface Timing
Figure 13.64 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 447 of 1064...
Page 487: Figure 13.65 Mpx Interface Timing
Figure 13.65 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 448 of 1064...
Page 488: Figure 13.66 Mpx Interface Timing
Figure 13.66 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 449 of 1064...
Page 489: Figure 13.67 Mpx Interface Timing
Figure 13.67 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 450 of 1064...
Page 490: Byte Control Sram Interface
32-byte boundary. The bus is not released during this period. Figure 13.68 shows an example of byte control SRAM connection to the SH7751 Series, and figures 13.69 to 13.71 show examples of byte control SRAM read cycles.
Page 491: Figure 13.69 Byte Control Sram Basic Read Cycle (No Wait)
CKIO A25–A0 D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.69 Byte Control SRAM Basic Read Cycle (No Wait) Rev. 3.0, 04/02, page 452 of 1064...
Page 492: Figure 13.70 Byte Control Sram Basic Read Cycle (One Internal Wait Cycle)
CKIO A25–A0 D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev. 3.0, 04/02, page 453 of 1064...
Page 493: Figure 13.71 Byte Control Sram Basic Read Cycle
CKIO A25–A0 D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev.
Page 494: 13.3.10 Waits Between Access Cycles
13.2.5, Wait Control Register 1 (WCR1). When the SH7751 Series performs consecutive write cycles, the data transfer direction is fixed (from the SH7751 Series to other memory) and there is no problem. With read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed.
Page 495: Figure 13.72 Waits Between Access Cycles
Twait Twait A25–A0 D31–D0 Area m space read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 13.72 Waits between Access Cycles Rev. 3.0, 04/02, page 456 of 1064...
Page 496: 13.3.11 Bus Arbitration
13.3.11 Bus Arbitration The SH7751 Series is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode.
Page 497 As the CPU in the SH7751 Series is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the SH7751 Series.
Page 498: Figure 13.73 Arbitration Sequence
Negated within 2 cycles A25–A0 D31–D0 (read) Slave mode device access Master access Slave access Master access Note: * For the SH7751, refer to the Usage Note in section 13.3.15. Figure 13.73 Arbitration Sequence Rev. 3.0, 04/02, page 459 of 1064...
Page 499: 13.3.12 Master Mode
signal is negated even while the signal is asserted to request the slave to relinquish the bus. When the SH7751 Series is used in master mode, consecutive bus accesses may be Rev. 3.0, 04/02, page 460 of 1064...
Page 500: 13.3.13 Slave Mode
Responsibility must also be assigned when a standby operation is performed to implement the power-down state. The design of the SH7751 Series provides for all control, including initialization, refreshing, and standby control, to be carried out by the master mode device.
Page 501: 13.3.15 Notes On Usage
If the SH7751 Series is specified as the master in a power-on reset, it will not accept bus requests from the slave until the enable bit (BCR1.BREQEN) is set to 1. To ensure that the slave processor does not access memory requiring initialization before use, such...
Page 502: Section 14 Direct Memory Access Controller (Dmac)
14.1 Overview The SH7751 Series includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (DMA transfer end notification), external memories, memory- mapped external devices, and on-chip peripheral modules (TMU, RTC, SCI, SCIF, CPG, and INTC).
Page 503 , ID [2:0], and D[31:0] pins. External requests can be accepted on all eight channels. Channel 0 does not have a request queue, but channels 1 to 3 in the SH7751 and channels 1 to 7 in the SH7751R each have four request queues.
Page 504 Channel 7 (SH7751R only): Single or dual address mode. External requests are accepted. In DDT mode, data transfer is carried out by the SH7751 using the K, ID [1:0], and D[31:0] signals to perform handshaking between the external ...
Page 505: Block Diagram (Sh7751)
14.1.2 Block Diagram (SH7751) Figure 14.1 shows a block diagram of the DMAC. DMAC module Count SARn control Register DARn control DMATCRn Activation On-chip control peripheral CHCRn module DMAOR Request priority SCI, SCIF control DACK0, DACK1 DRAK0, DRAK1 interface SAR0, DAR0, DMATCR0,...
Page 506: Pin Configuration (Sh7751)
14.1.3 Pin Configuration (SH7751) Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel Pin Name Abbreviation Function DMA transfer Input DMA transfer request input from request external device to channel 0 acceptance DRAK0 Output...
Page 507: Register Configuration (Sh7751)
(ID [1] = DRAK1, ID [0] = DACK1) 14.1.4 Register Configuration (SH7751) Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers are allocated to each channel, and an additional control register is shared by all four channels.
Page 508 Table 14.3 DMAC Registers (cont) Chan- Abbre- Read/ Area 7 Access Name viation Write Initial Value P4 Address Address Size DMA source Undefined H'FFA00010 H'1FA00010 32 SAR1 address register 1 DMA destination Undefined H'FFA00014 H'1FA00014 32 DAR1 address register 1 DMA transfer DMATCR1 R/W Undefined...
Page 509: Register Descriptions
14.2 Register Descriptions 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Initial value: —...
Page 510: Dma Destination Address Registers 0-3 (Dar0-Dar3)
14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Initial value: —...
Page 511: Dma Transfer Count Registers 0-3 (Dmatcr0-Dmatcr3)
14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: Initial value: R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — —...
Page 512: Dma Channel Control Registers 0-3 (Chcr0-Chcr3)
14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: SSA2 SSA1 SSA0 DSA2 DSA1 DSA0 Initial value: R/W: Bit: — — — — Initial value: — — — — R/W: (R/W) (R/W) Bit: Initial value: R/W: Bit: — Initial value: R/W: R/(W) Notes: The TE bit can only be written with 0 after being read as 1, to clear the flag.
Page 513 Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for PCMCIA interface area access. Bit 31: SSA2 Bit 30: SSA1 Bit 29: SSA0 Description Reserved in PCMCIA access (Initial value) Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space...
Page 514 Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for PCMCIA interface area access. Bit 27: DSA2 Bit 26: DSA1 Bit 25: DSA0 Description Reserved in PCMCIA access (Initial value) Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space...
Page 515 Bit 19— Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR3.
Page 516 Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode.
Page 517 Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: Bit 8: Description External request, dual address mode* (external address space external address space) (Initial value) Setting prohibited External request, single address mode External address space external device*...
Page 518 Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. Bit 7: TM Description Cycle steal mode (Initial value) Burst mode Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. In access to external memory, the specification is treated as an access size as described in section 13.3, Operation.
Page 519 Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1.
Page 520: Dma Operation Register (Dmaor)
14.2.5 DMA Operation Register (DMAOR) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — Initial value: R/W: Bit: — —...
Page 521 Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. Bit 9: PR1 Bit 8: PR0 Description...
Page 522: Operation
Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended.
Page 523 Note: If a transfer request is issued while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. Transfer is started when subsequently enabled (by setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). Rev.
Page 524: Figure 14.2 Dmac Transfer Flowchart
Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1? Illegal address check (reflected in AE bit) NMIF, AE, TE = 0? Transfer request issued? Bus mode, transfer request mode, detection method Transfer (1 transfer unit) DMATCR - 1 → DMATCR Update SAR, DAR NMIF or DMATCR = 0?
Page 525: Dma Transfer Requests
14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.
Page 526: Table 14.4 Selecting External Request Mode With Rs Bits
Table 14.4 Selecting External Request Mode with RS Bits Address Mode Transfer Source Transfer Destination Dual address External memory, External memory, mode memory-mapped memory-mapped external device, or external device, or external device with external device with DACK DACK Single address External memory External device mode...
Page 527 On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit (TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the two serial communication interfaces (SCI, SCIF).
Page 528: Table 14.5 Selecting On-Chip Peripheral Module Request Mode With Rs Bits
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits DMAC Transfer DMAC Transfer Transfer Transfer RS3 RS2 RS1 RS0 Request Source Request Signal Source Destination Bus Mode SCI transmitter SCTDR1 (SCI External* SCTDR1 Cycle steal transmit-data- mode empty transfer request) SCI receiver SCRDR1 (SCI...
Page 529: Channel Priorities
14.3.3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. The mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In this mode, the relative channel priorities remain fixed.
Page 530: Figure 14.3 Round Robin Mode
Transfer on channel 0 Channel 0 is given the lowest CH0 > CH1 > CH2 > CH3 Initial priority order priority. CH1 > CH2 > CH3 > CH0 Priority order after transfer Transfer on channel 1 When channel 1 is given the Initial priority order CH0 >...
Page 531: Figure 14.4 Example Of Changes In Priority Order In Round Robin Mode
1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby).
Page 532: Types Of Dma Transfer
14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output.
Page 533: Figure 14.5 Data Flow In Single Address Mode
DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. External External address data bus SH7751 Series External memory DMAC External device with DACK DACK : Data flow Figure 14.5 Data Flow in Single Address Mode...
Page 534: Figure 14.6 Dma Transfer Timing In Single Address Mode
CKIO Address output to external memory A28–A0 space Data output from external device D63–D0 with DACK DACK DACK signal to external device with DACK WE signal to external memory space (a) From external device with DACK to external memory space CKIO Address output to external memory A28–A0...
Page 535: Figure 14.7 Operation In Dual Address Mode
Dual Address Mode: Dual address mode is used to access both the transfer source and the transfer destination by address. The transfer source and destination can be accessed by either on- chip peripheral module or external address. In dual address mode, data is read from the transfer source in the data read cycle, and written to the transfer destination in the data write cycle, so that the transfer is executed in two bus cycles.
Page 536: Figure 14.8 Example Of Transfer Timing In Dual Address Mode
CKIO Transfer source Transfer destination A28–A0 address address D63–D0 DACK Data read cycle Data write cycle (1st cycle) (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0–...
Page 537: Figure 14.9 Example Of Dma Transfer In Cycle Steal Mode
Bus returned to CPU Bus cycle DMAC DMAC DMAC DMAC Read Write Read Write Figure 14.9 Example of DMA Transfer in Cycle Steal Mode Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied.
Page 538: Table 14.7 Relationship Between Dma Transfer Type, Request Mode, And Bus Mode
Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the bus mode. Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Request Transfer Size...
Page 539: Table 14.8 External Request Transfer Sources And Destinations In Normal Mode
(a) Normal DMA Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7751 Series in normal DMA mode. Table 14.8 External Request Transfer Sources and Destinations in Normal Mode...
Page 540: Table 14.9 External Request Transfer Sources And Destinations In Ddt Mode
(b) DDT Mode Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7751 Series in DDT mode. Table 14.9 External Request Transfer Sources and Destinations in DDT Mode...
Page 541: Types Of Dma Transfer
Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the CPU until channel 1 transfer ends. DMAC CH1 DMAC CH1 DMAC CH0...
Page 542 1. Cycle Steal Mode In cycle steal mode, The sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation.
Page 543 In figure 14.22, with a 32-byte data size, 32-bit bus width, and SDRAM: row hit write, DMAC transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second sampling operation begins one cycle after DACK is asserted for the first DMAC transfer. 4.
Page 544: Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus External Bus
Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus External Bus/ (Level Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 505 of 1064...
Page 545: Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus External Bus
Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus External Bus/ (Edge Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 506 of 1064...
Page 546: Figure 14.14 Dual Address Mode/Burst Mode External Bus External Bus Level Detection), Dack (Read Cycle)
Figure 14.14 Dual Address Mode/Burst Mode External Bus External Bus/ (Level Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 507 of 1064...
Page 547: Edge Detection), Dack (Read Cycle)
Figure 14.15 Dual Address Mode/Burst Mode External Bus External Bus/ (Edge Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 508 of 1064...
Page 548: Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip Sci (Level Detection External Bus
Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) External Bus Rev. 3.0, 04/02, page 509 of 1064...
Page 549 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus On-Chip SCI (Level Detection) Rev. 3.0, 04/02, page 510 of 1064...
Page 550 Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus External Bus/ (Level Detection) Rev. 3.0, 04/02, page 511 of 1064...
Page 551 Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus External Bus/ (Edge Detection) Rev. 3.0, 04/02, page 512 of 1064...
Page 552 Figure 14.20 Single Address Mode/Burst Mode External Bus External Bus/ (Level Detection) Rev. 3.0, 04/02, page 513 of 1064...
Page 553 Figure 14.21 Single Address Mode/Burst Mode External Bus External Bus/ (Edge Detection) Rev. 3.0, 04/02, page 514 of 1064...
Page 554: Figure 14.22 Single Address Mode/Burst Mode External Bus External Bus
Figure 14.22 Single Address Mode/Burst Mode External Bus External Bus/ (Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM: Row Hit Write) Rev. 3.0, 04/02, page 515 of 1064...
Page 555: Ending Dma Transfer
14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer.
Page 556 Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: The value in the DMA transfer count register (DMATCR) reaches 0. The DE bit in the DMA channel control register (CHCR) is cleared to 0. 1.
Page 557 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU.
Page 558: Examples Of Use
14.4 Examples of Use 14.4.1 Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here. Table 14.10 shows the transfer conditions and the corresponding register settings. Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings Transfer Conditions...
Page 559: On-Demand Data Transfer Mode (Ddt Mode)
14.5 On-Demand Data Transfer Mode (DDT Mode) 14.5.1 Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to transfer to channel 0 to 3 via the data bus and DDT module, ...
Page 560 1. Normal data transfer mode (channel 0) (the data bus available signal) is asserted in response to (the data bus request signal) from an external device. Two CKIO-synchronous cycles after is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with (the transfer request signal).
Page 561: Pins In Ddt Mode
14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. /DRAK0 /DACK0 SH7751 Series ID1, ID0/DRAK1, DACK1 External device D31–D0 = DTR A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode...
Page 562: Figure 14.25 Data Transfer Request Format
: Reply strobe signal for external device from DMAC The assertion timing is the same as the DACKn assertion timing for each memory interface. However, note that is an active-low signal. ID1, ID0: Channel number notification signals 00: Channel 0 01: Channel 1 10: Channel 2...
Page 563: Table 14.11 Usable Sz, Id, And Md Combination In Ddt Mode
101, 110. Usable SZ, ID, and MD Combination in DDT Mode Table 14.11 shows the usable combination of SZ, ID, and MD in DDT mode of the SH7751. Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode SZ [2:0]...
Page 564: Transfer Request Acceptance On Each Channel
14.5.3 Transfer Request Acceptance on Each Channel On channel 0, a DMA data transfer request can be made by means of the DTR format. No further transfer requests are accepted between DTR format acceptance and the end of the data transfer. On channels 1 to 3, output a transfer request from an external device by means of the DTR format (ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal DMA mode.
Page 565: Figure 14.26 Single Address Mode/Synchronous Dram External Device Longword Transfer Sdram Auto-Precharge Read Bus Cycle, Burst (Rcd=1, Cas Latency=3, Tpc=3)
Figure 14.26 Single Address Mode/Synchronous DRAM External Device Longword Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS latency=3, TPC=3) Rev. 3.0, 04/02, page 526 of 1064...
Page 566: Figure 14.27 Single Address Mode/External Device Synchronous Dram Longword Transfer Sdram Auto-Precharge Write Bus Cycle, Burst (Rcd=1, Trwl=2, Tpc=1)
Figure 14.27 Single Address Mode/External Device Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1, TRWL=2, TPC=1) Rev. 3.0, 04/02, page 527 of 1064...
Page 567: Figure 14.28 Dual Address Mode/Synchronous Dram Sram Longword Transfer
Figure 14.28 Dual Address Mode/Synchronous DRAM SRAM Longword Transfer Rev. 3.0, 04/02, page 528 of 1064...
Page 568: Figure 14.29 Single Address Mode/Burst Mode/External Bus External Device 32-Byte
CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.29 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.30 Single Address Mode/Burst Mode/External Device External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.
Page 569: Figure 14.31 Single Address Mode/Burst Mode/External Bus External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer
CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 Figure 14.31 Single Address Mode/Burst Mode/External Bus External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 3.0, 04/02, page 530 of 1064...
Page 570: Figure 14.32 Single Address Mode/Burst Mode/External Device External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer
CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 Figure 14.32 Single Address Mode/Burst Mode/External Device External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 3.0, 04/02, page 531 of 1064...
Page 571: Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer)
CKIO DBREQ BAVL A25–A0 D31–D0 MD = 00 MD = 00 TDACK ID1, ID0 Start of data transfer Next transfer request Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) Rev. 3.0, 04/02, page 532 of 1064...
Page 572: Figure 14.34 Handshake Protocol Without Use Of Data Bus
CKIO DBREQ BAVL A25–A0 D31–D0 MD = 00 TDACK ID1, ID0 Start of data transfer Next transfer request Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) Rev. 3.0, 04/02, page 533 of 1064...
Page 573: Figure 14.35 Read From Synchronous Dram Precharge Bank
CKIO DBREQ BAVL A25–A0 D2 D3 D31–D0 RAS, CAS, Figure 14.35 Read from Synchronous DRAM Precharge Bank CKIO DBREQ Transfer requests can be accepted BAVL A25–A0 D31–D0 RAS, CAS, Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) Rev. 3.0, 04/02, page 534 of 1064...
Page 574: Figure 14.37 Read From Synchronous Dram (Row Hit)
CKIO DBREQ BAVL A25–A0 D31–D0 D2 D3 RAS, CAS, Figure 14.37 Read from Synchronous DRAM (Row Hit) CKIO DBREQ BAVL A25–A0 D31–D0 D2 D3 RAS, CAS, Figure 14.38 Write to Synchronous DRAM Precharge Bank Rev. 3.0, 04/02, page 535 of 1064...
Page 575: Figure 14.39 Write To Synchronous Dram Non-Precharge Bank (Row Miss)
CKIO DBREQ Transfer requests can be accepted BAVL A25–A0 D31–D0 RAS, CAS, Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, Figure 14.40 Write to Synchronous DRAM (Row Hit) Rev. 3.0, 04/02, page 536 of 1064...
Page 576: Figure 14.41 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer
CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.41 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev. 3.0, 04/02, page 537 of 1064...
Page 577: Figure 14.42 Ddt Mode Setting
DMA Operation Register (DMAOR) PR[1:0] NMIF DDT: 0: Normal DMA mode 1: On-demand data transfer mode Figure 14.42 DDT Mode Setting CKIO DBREQ BAVL No DMA request sampling A25–A0 D31–D0 D1 D2 D3 D1 D2 TDACK ID1, ID0 Start of data transfer Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device External Bus Data Transfer...
Page 578: Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus External Device Data Transfer
CKIO DBREQ BAVL Wait for next DMA request