Hitachi SH7750 Hardware Manual page 617

CLK
A25–A0 RA CA
D63–D0 D0 D1 D2 D3 D4 D5 D6 D7
RAS,
BA RD
CAS, WE
ID1, ID0
10
No DTR cycle, so requests can be made at any time
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/
External Bus → → → → External Device Data Transfer/
Direct Data Transfer Request to Channel 2 without Using Data Bus
Rev. 6.0, 07/02, page 567 of 986