Interrupt Source Register 00 (Intreq00) (Sh7750R Only); Table 19.7 Interrupt Request Sources And The Bits Of The Intpri00 Register - Hitachi SH7750 Hardware Manual

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priority-level

Note: As shown in the table above, levels for all eight on-chip peripheral modules are assigned in

a single register. The interrupt priority level for the interrupt source that corresponds to each

set of four bits is set as a value from H'F (1111) to H'0 (0000). The setting H'F selects

interrupt priority level 15, which is the highest, and H'0 selects level 0, which means that

interrupt requests from that source are masked.

Reserved bits are always read as 0. When writing, only 0s should be written to these bits.

Interrupt Source Register 00 (INTREQ00) (SH7750R Only)

The interrupt source register 00 (INTREQ00) indicates the origin of the interrupt request that has

been sent to the INTC. The states of the bits in this register is not affected by masking of the

corresponding interrupts by the settings in the INTPRI00 or INTMSK00 register. INTREQ00 is a

32-bit read-only register.

Initial value:

Initial value:

Bit 31 to 0—Interrupt Request: Each of the non-reserved bits in this register indicates that there

is an interrupt request relevant to that bit. For the correspondence between the bits and interrupt

sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00

(SH7750R Only).

Bits 31 to 0

There is no interrupt request that corresponds to this bit

There is an interrupt request that corresponds to this bit.

TMU ch4 TMU ch3 Reserved

Rev. 6.0, 07/02, page 765 of 986

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