Figure 3.11 Flowchart Of Memory Access Using Itlb - Hitachi SH7750 Hardware Manual

VA is VA is
in P4 area in P2 area
0
Access prohibited
No
Search UTLB
Yes
Match?
No
Instruction TLB
miss exception
Instruction TLB protection
violation exception

Figure 3.11 Flowchart of Memory Access Using ITLB

Instruction access to virtual address (VA)
VA is
in P1 area
CCR.ICE?
1
VPNs match
and V = 1
Yes
Hardware ITLB
miss handling
Record in ITLB
0
PR?
C = 1
and CCR.ICE = 1
Cache access
VA is in P0, U0,
or P3 area
No
MMUCR.AT = 1
Yes
SH = 0
No
and (MMUCR.SV = 0 or
SR.MD = 0)
Yes
VPNs match
No
and ASIDs match and
V = 1
Yes
Only one
entry matches
Yes
SR.MD?
0 (User)
1 (Privileged)
1
No
Yes
Rev. 6.0, 07/02, page 77 of 986
No
Instruction TLB
multiple hit exception
Memory access
(Non-cacheable)