Page 1 Hitachi SuperH™ RISC engine SH7750 Series SH7750, SH7750S Hardware Manual ADE-602-124C Rev. 4.0 4/21/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 Preface The SH-4 (SH7750 Series (SH7750, SH7750S)) has been developed as the top-end model in the SuperH™ RISC engine family, featuring a 128-bit graphic engine for multimedia applications and 360 MIPS performance. The SH7750 Series CPU has a RISC type instruction set, and features upward-compatibility at the object code level with SH-1, SH-2, SH-3, and SH-3E microcomputers.
Page 4 Revisions and Additions in this Edition Page Item Revisions (See Manual for Details) 1.1 SH7750 Features 167 MHz and 128 MHz operating Table 1.1 frequency versions added 5.3.1 Exception Handling Flow • R15 added to description • Save general register 15 (SGR) added to description •...
Page 5 Page Item Revision (See Manual for Details) 386 to 391 13.3.8 MPX Interface MPX interface timing conditions amended Figures 13.52 to 13.59 687, 688 22.2.2 Pin Functions (208-Pin QFP) Table amended Table 22.2 Pin Functions Pin nos. 137, 139, 141, 145 Data amended to data/port Section 23 Electronical Characteristics HD6417750BP200H,...
Page 6: Table Of Contents
Contents Section 1 Overview ......................SH7750 Series Features ....................Block Diagram ........................Section 2 Programming Model ..................Data Formats........................Register Configuration...................... 10 2.2.1 Privileged Mode and Banks ................. 10 2.2.2 General Registers ....................13 2.2.3 Floating-Point Registers..................15 2.2.4 Control Registers ....................17 2.2.5...
Page 7 3.5.2 MMU Software Management ................45 3.5.3 MMU Instruction (LDTLB)................. 45 3.5.4 Hardware ITLB Miss Handling ................46 3.5.5 Avoiding Synonym Problems ................47 MMU Exceptions......................48 3.6.1 Instruction TLB Multiple Hit Exception.............. 48 3.6.2 Instruction TLB Miss Exception................49 3.6.3 Instruction TLB Protection Violation Exception ..........
Page 8 4.5.4 OC Data Array ..................... 78 Store Queues ........................79 4.6.1 SQ Configuration....................79 4.6.2 SQ Writes......................79 4.6.3 Transfer to External Memory................79 4.6.4 SQ Protection....................... 81 Section 5 Exceptions ......................83 Overview........................... 83 5.1.1 Features........................ 83 5.1.2 Register Configuration..................83 Register Descriptions ......................
Page 9 6.6.2 Pair Single-Precision Data Transfer..............128 Section 7 Instruction Set ....................129 Execution Environment ....................129 Addressing Modes ......................131 Instruction Set ........................135 Section 8 Pipelining ......................149 Pipelines..........................149 Parallel-Executability......................156 Execution Cycles and Pipeline Stalling ................160 Section 9 Power-Down Modes ..................
Page 10 10.1.1 Features........................ 197 10.2 Overview of CPG......................199 10.2.1 Block Diagram of CPG..................199 10.2.2 CPG Pin Configuration ..................201 10.2.3 CPG Register Configuration ................201 10.3 Clock Operating Modes ....................202 10.4 CPG Register Description ....................203 10.4.1 Frequency Control Register (FRQCR)..............203 10.5 Changing the Frequency ....................
Page 11 11.2.8 Year Counter (RYRCNT) ..................225 11.2.9 Second Alarm Register (RSECAR) ..............226 11.2.10 Minute Alarm Register (RMINAR) ..............226 11.2.11 Hour Alarm Register (RHRAR) ................227 11.2.12 Day-of-Week Alarm Register (RWKAR)............227 11.2.13 Day Alarm Register (RDAYAR) ................. 228 11.2.14 Month Alarm Register (RMONAR) ..............
Page 12 13.1.1 Features........................ 257 13.1.2 Block Diagram..................... 259 13.1.3 Pin Configuration....................260 13.1.4 Register Configuration..................264 13.1.5 Overview of Areas ....................265 13.1.6 PCMCIA Support ....................268 13.2 Register Descriptions ......................272 13.2.1 Bus Control Register 1 (BCR1) ................272 13.2.2 Bus Control Register 2 (BCR2) ................280 13.2.3 Wait Control Register 1 (WCR1).................
Page 13 14.1.4 Register Configuration..................423 14.2 Register Descriptions ......................425 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......... 425 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)........426 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......427 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)........428 14.2.5 DMA Operation Register (DMAOR)..............
Page 14 15.3.3 Multiprocessor Communication Function ............543 15.3.4 Operation in Synchronous Mode ................. 551 15.4 SCI Interrupt Sources and DMAC ..................560 15.5 Usage Notes ........................561 Section 16 Serial Communication Interface with FIFO (SCIF) ......565 16.1 Overview........................... 565 16.1.1 Features........................ 565 16.1.2 Block Diagram.....................
Page 15 17.3.2 Pin Connections ....................619 17.3.3 Data Format ......................620 17.3.4 Register Settings ....................621 17.3.5 Clock........................623 17.3.6 Data Transfer Operations..................626 17.4 Usage Notes ........................633 Section 18 I/O Ports ......................639 18.1 Overview........................... 639 18.1.1 Features........................ 639 18.1.2 Block Diagrams ....................
Page 16 20.6.1 Transition to User Break Controller Stopped State..........701 20.6.2 Cancelling the User Break Controller Stopped State ........... 701 20.6.3 Examples of Stopping and Restarting the User Break Controller......702 Section 21 Hitachi User Debug Interface (H-UDI) ........... 703 21.1 Overview........................... 703 21.1.1 Features........................
Page 17 21.2.3 Bypass Register (SDBPR) ................... 708 21.3 Operation .......................... 709 21.3.1 TAP Control......................709 21.3.2 H-UDI Reset ......................710 21.3.3 H-UDI Interrupt ....................710 21.3.4 Bypass........................710 21.4 Usage Notes ........................711 Section 22 Pin Description ....................713 22.1 Pin Arrangement ....................... 713 22.2 Pin Functions ........................
Page 18: Overview
MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The SH7750 Series has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
Page 19 Table 1.1 SH7750 Series Features (cont) Item Features • Original Hitachi SH architecture • 32-bit internal data bus • General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers •...
Page 20 Table 1.1 SH7750 Series Features (cont) Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero •...
Page 21 Table 1.1 SH7750 Series Features (cont) Item Features • Clock pulse Choice of main clock: 1/2, 1, 3, or 6 times EXTAL generator (CPG) • Clock modes:  CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock: maximum 200 MHz ...
Page 22 Table 1.1 SH7750 Series Features (cont) Item Features • Cache memory Instruction cache (IC)  8 kbytes, direct mapping  256 entries, 32-byte block length  Normal mode (8-kbyte cache)  Index mode • Operand cache (OC)  16 kbytes, direct mapping ...
Page 23 Table 1.1 SH7750 Series Features (cont) Item Features • Bus state Supports external memory access controller (BSC)  64/32/16/8-bit external data bus • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: ...
Page 24 Table 1.1 SH7750 Series Features (cont) Item Features • Serial Two full-duplex communication channels (SCI, SCIF) communication • Channel 1 (SCI): interface  Choice of asynchronous mode or synchronous mode (SCI, SCIF)  Supports smart card interface • Channel 2 (SCIF): ...
Page 25: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram of the SH7750 Series. Lower 32-bit data Lower 32-bit data I cache O cache ITLB UTLB (8 kB) (16 kB) INTC DMAC (SCIF) External bus interface 26-bit 64-bit address data BSC:...
Page 26: Programming Model
Section 2 Programming Model Data Formats The data formats handled by the SH7750 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 27: Register Configuration
Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH7750 has two processor modes, user mode and privileged mode. The SH7750 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processor modes.
Page 28: General Registers
Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.
Page 29 R0 _ BANK0* R0 _ BANK1* R0 _ BANK0* R1 _ BANK0* R1 _ BANK1* R1 _ BANK0* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK1* R3 _ BANK0* R4 _ BANK0* R4 _ BANK0* R4 _ BANK1* R5 _ BANK0* R5 _ BANK0*...
Page 30 R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7750 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
Page 31 SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...
Page 32: Floating-Point Registers
2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Page 33 • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10...
Page 34: Control Registers
Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 16 15 14 —...
Page 35: System Registers
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 36 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 37: Memory-Mapped Registers
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 38: Data Format In Registers
Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Data Format in Registers Register operands are always longwords (32 bits).
Page 39: Processor States
Little endian Figure 2.5 Data Formats In Memory Note: The SH7750 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed.
Page 40 Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 9, Power-Down Modes.
Page 41: Processor Modes
Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1.
Page 42: Memory Management Unit (Mmu)
(translation lookaside buffer: TLB). The SH7750 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte).
Page 43 (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7750 Series is referred to as virtual address space, and the address space in physical memory as physical address space.
Page 44 Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev. 4.0, 04/00, page 27 of 850...
Page 45: Register Configuration
3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Name tion Value* Address* Address* Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register Page table entry low PTEL Undefined H'FF00 0004 H'1F00 0004 32...
Page 46: Register Descriptions
Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.
Page 47 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware.
Page 48 instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software.
Page 49: Memory Space
3.3.1 Physical Memory Space The SH7750 Series supports a 32-bit physical memory space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical memory space. The physical memory space is divided into a number of areas, as shown in figure 3.3.
Page 50: External Memory Space
P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4.
Page 51 H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000 Operand cache data array H'F600 0000...
Page 52 3.3.2 External Memory Space The SH7750 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC).
Page 53: Virtual Memory Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH7750 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1- Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.
Page 54: On-Chip Ram Space
3.3.4 On-Chip RAM Space In the SH7750 Series, half (8 kbytes) of the instruction cache (16 kbytes) can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area.
Page 55: Single Virtual Memory Mode And Multiple Virtual Memory Mode
address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either...
Page 56 Entry 0 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 1 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 2 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 63 ASID [7:0] VPN [31:10] V...
Page 57 • ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed.
Page 58 • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1.
Page 59: Instruction Tlb (Itlb) Configuration
3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries.
Page 60 Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match...
Page 61 Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match VPNs match...
Page 62: Mmu Functions
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7750 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.
Page 63: Hardware Itlb Miss Handling
3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7750 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB.
Page 64: Avoiding Synonym Problems
This problem does not occur with the instruction TLB or instruction cache . In the SH7750 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4- kbyte page, are subject to address translation.
Page 65: Mmu Exceptions
MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 66: Instruction Tlb Miss Exception
3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below.
Page 67: Instruction Tlb Protection Violation Exception
3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.
Page 68: Data Tlb Multiple Hit Exception
3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.
Page 69: Data Tlb Protection Violation Exception
Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry.
Page 70: Initial Page Write Exception
Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains...
Page 71: Memory-Mapped Tlb Configuration
Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3.
Page 72: Itlb Address Array
3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field.
Page 73: Itlb Data Array 1
3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.
Page 74: Itlb Data Array 2
3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 75 In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0].
Page 76: Utlb Data Array 1
3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field.
Page 77: Utlb Data Array 2
3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 78: Caches
4.1.1 Features The SH7750 Series has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) can also be used as on-chip RAM. The features of these caches are summarized in table 4.1.
Page 79: Register Configuration
4.1.2 Register Configuration Table 4.2 shows the cache control registers. Table 4.2 Cache Control Registers Initial Area 7 Access Name Abbreviation R/W Value* Address* Address* Size Cache control H'0000 0000 H'FF00 001C H'1F00 001C register Queue address QACR0 Undefined H'FF00 0038 H'1F00 0038 control register 0 Queue address...
Page 80 (1) Cache Control Register (CCR): CCR contains the following bits: IIX: IC index enable ICI: IC invalidation ICE: IC enable OIX: OC index enable ORA: OC RAM enable OCI: OC invalidation Copy-back enable Write-through enable OCE: OC enable Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in area 7.
Page 81 • OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode •...
Page 82: Operand Cache (Oc)
Operand Cache (OC) 4.3.1 Configuration Figure 4.2 shows the configuration of the operand cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 RAM area determination [11:5] [13] [12] Longword (LW) selection Address array Data array 19 bits 1 bit 1 bit 32 bits...
Page 83: Read Operation
The operand cache consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32- byte data. • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 84: Write Operation
3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address.
Page 85 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. 3b.
Page 86: Write-Back Buffer
4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, the SH7750 Series has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination.
Page 87: Oc Index Mode
• When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 kB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 kB): Corresponds to RAM area 1 RAM areas 1 and 2 then repeat every 8 kbytes up to H'7FFF FFFF.
Page 88: Coherency Between Cache And External Memory
Prefetch Operation The SH7750 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance.
Page 89: Instruction Cache (Ic)
Instruction Cache (IC) 4.4.1 Configuration Figure 4.5 shows the configuration of the instruction cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 [11:5] [12] Longword (LW) selection Address array Data array 19 bits 1 bit 32 bits 32 bits 32 bits...
Page 90: Read Operation
The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32- byte data (16 instructions). • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 91: Ic Index Mode
4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two 4-kbyte areas by means of effective address bit [25], providing efficient use of the cache.
Page 92: Ic Data Array
2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3.
Page 93: Oc Address Array
The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2.
Page 94 The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0.
Page 95: Oc Data Array
4.5.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field.
Page 96: Store Queues
Store Queues The SH7750 Series supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S, if the SQs are not used the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.
Page 97 memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external memory address bit [28:0] specification is as shown below, according to whether the MMU is on or off.
Page 98: Sq Protection
4.6.4 SQ Protection Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. If an exception occurs in an SQ write, the SQ contents may be corrupted. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted.
Page 99: Exceptions
SH7750 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1.
Page 100: Register Descriptions
Register Descriptions There are three registers related to exception handling. These are allocated to memory, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.
Page 101: Exception Handling Functions
Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 102: Exception Types And Priorities
Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Reset Abort type Power-on reset H'A000 0000 —...
Page 103 Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340...
Page 104: Exception Flow
Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral DMAC DMTE0 (VBR) H'600 H'640 type module DMTE1 H'660 interrupt DMTE2 H'680 (module/ source) DMTE3 H'6A0 DMAE H'6C0 SCIF H'700 H'720 H'740...
Page 105: Exception Source Acceptance
Reset requested? Execute next instruction Is highest- General priority exception exception requested? re-exception type? Cancel instruction execution result Interrupt requested? SSR ← SR EXPEVT ← exception code SPC ← PC SR. {MD, RB, BL, FD, IMASK} ← 11101111 SGR ← R15 PC ←...
Page 106 Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Instruction fetch ID: Instruction decode EX: Instruction execution Instruction n+3 MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling:...
Page 107: Exception Requests And Bl Bit
5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 108: Resets
5.6.1 Resets (1) Power-On Reset • Sources:  SCK2 pin high level and 5(6(7 pin low level  When the watchdog timer overflows while the WT/,7 bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. •...
Page 109 (2) Manual Reset • Sources:  SCK2 pin low level and 5(6(7 pin low level  When a general exception other than a user break occurs while the BL bit is set to 1 in SR  When the watchdog timer overflows while the WT/,7 bit and RSTS bit are both set to 1 in WTCSR.
Page 110 (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111.
Page 111 (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 112 (5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 113: General Exceptions
5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 114 (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 115 (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 116 (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible Read/write access possible...
Page 117 (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H'0000 0100 •...
Page 118 (6) Data Address Error • Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)  Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ...
Page 119 (7) Instruction Address Error • Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 120 (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 121 (9) General Illegal Instruction Exception • Sources:  Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 122 (10) Slot Illegal Instruction Exception • Sources:  Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR ...
Page 123 (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 124 (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 125 (13) User Breakpoint Trap • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'0000 0100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 126 (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 127: Interrupts
5.6.3 Interrupts (1) NMI • Source: NMI pin edge detection • Transition address: VBR + H'0000 0600 • Transition operations: The contents of PC and SR immediately after the instruction at which this interrupt was accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 128 (2) IRL Interrupts • Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'0000 0600 • Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC.
Page 129 (3) Peripheral Module Interrupts • Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). •...
Page 130: Priority Order With Multiple Exceptions
5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 131: Usage Notes
Usage Notes 1. Return from exception handling a. Check the BL bit in SR with software. If SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR contents are set in SR, and branch is made to the SPC address to return from the exception handling routine.
Page 132: Restrictions
Restrictions 1. Restrictions on first instruction of exception handling routine • Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. • When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register.
Page 133: Floating-Point Unit
A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) The SH7750 Series can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 23 22 Figure 6.1 Format of Single-Precision Floating-Point Number...
Page 134 52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1. The two values E –...
Page 135: Non-Numbers (Nan)
Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000 Positive normalized H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to number H'00100000 00000000 Positive denormalized...
Page 136: Denormalized Numbers
EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7750 Series as operation results are as follows: • Single-precision qNaN: H'7FBFFFFF •...
Page 137: Registers
Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;...
Page 138 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14 FPR15_BANK0 FR15 XF15 FPR0_BANK1...
Page 139: Floating-Point Status/Control Register (Fpscr)
6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 140: Floating-Point Communication Register (Fpul)
• Bits 22 to 31: Reserved These bits are always read as 0, and should only be written with 0. Notes: The following functions have been added to the FPU of the SH7750 Series (not provided in the FPU of the SH7718): 1.
Page 141: Floating-Point Exceptions
0, but the corresponding bit in the flag field remains unchanged. • Enable/disable exception handling The SH7750 Series supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases:  FPU error (E): FPSCR.DN = 0 and a denormalized number is input ...
Page 142: Graphics Support Functions
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.  Inexact exception (I): An inexact result is generated. Graphics Support Functions The SH7750 Series supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations.
Page 143 This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 × 4 matrix, the SH7750 Series supports 4-dimensional operations. • Matrix (4 × 4) × matrix (4 × 4): This operation requires the execution of four FTRV instructions.
Page 144: Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, the SH7750 Series also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the SH7750 Series can perform data transfer by means of pair single- precision data transfer instructions. • FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) •...
Page 145: Instruction Set
PC: At the start of instruction execution, PC indicates the address of the instruction itself. Data sizes and data types: The SH7750 Series’ instruction set is implemented with 16-bit fixed- length instructions. The SH7750 Series can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access.
Page 146 In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution.
Page 147: Addressing Modes
Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 148 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), Word: Rn +...
Page 149 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size.
Page 150 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp × 2 → Branch- disp added after being sign-extended and multiplied by 2.
Page 151: Instruction Set
Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand →, ← Summary of Transfer direction operation...
Page 152 Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — (disp × 2 + PC + 4) → sign MOV.W @(disp,PC),Rn 1001nnnndddddddd — — extension → Rn (disp × 4 + PC & H'FFFFFFFC MOV.L @(disp,PC),Rn 1101nnnndddddddd —...
Page 153 Table 7.3 Fixed-Point Transfer Instructions (cont) Instruction Operation Instruction Code Privileged T Bit R0 → (disp + GBR) MOV.B R0,@(disp,GBR) 11000000dddddddd — — R0 → (disp × 2 + GBR) MOV.W R0,@(disp,GBR) 11000001dddddddd — — R0 → (disp × 4 + GBR) MOV.L R0,@(disp,GBR) 11000010dddddddd —...
Page 154 Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100 — — Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii — — Rn + Rm + T → Rn, carry → T ADDC Rm,Rn 0011nnnnmmmm1110 —...
Page 155 Table 7.4 Arithmetic Operation Instructions (cont) Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word → Rn EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte → Rn EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 —...
Page 156 Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —...
Page 157 Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — LSB → Rn → T ROTR 0100nnnn00000101 — T ← Rn ← T ROTCL 0100nnnn00100100 — T → Rn → T ROTCR 0100nnnn00100101 —...
Page 158 Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — 4 → PC When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd —...
Page 159 Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit 0 → MACH, MACL CLRMAC 0000000000101000 — — 0 → S CLRS 0000000001001000 — — 0 → T CLRT 0000000000001000 — Rm → SR Rm,SR 0100mmmm00001110 Privileged Rm → GBR Rm,GBR 0100mmmm00011110 —...
Page 160 Table 7.8 System Control Instructions (cont) Instruction Operation Instruction Code Privileged T Bit 1 → S SETS 0000000001011000 — — 1 → T SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR → Rn SR,Rn 0000nnnn00000010 Privileged — GBR →...
Page 161 Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H'00000000 → FRn FLDI0 1111nnnn10001101 — — H'3F800000 → FRn FLDI1 1111nnnn10011101 — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — — (Rm) → FRn FMOV.S @Rm,FRn 1111nnnnmmmm1000 — —...
Page 162 Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — FFFF → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 — — When DRn = DRm, 1 → T FCMP/EQ DRm,DRn 1111nnn0mmm00100 —...
Page 163 Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn 1111nnn1mmm01100 — — XDm → DRn FMOV XDm,DRn 1111nnn0mmm11100 — — XDm → XDn FMOV XDm,XDn 1111nnn1mmm11100 — — (Rm) → XDn FMOV @Rm,XDn 1111nnn1mmmm1000 —...
Page 164: Pipelining
Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7750 Series. Pipelines Figure 8.1 shows the basic pipelines.
Page 165 1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction • Address •...
Page 166 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.
Page 167 10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.
Page 168 19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.
Page 169 31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.
Page 170 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle Notes: : Cannot overlap a stage of the same kind, except when two instructions are executed in parallel.
Page 171: Parallel-Executability
Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.
Page 172 Table 8.1 Instruction Groups (cont) 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W...
Page 173 Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV...
Page 174 Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L...
Page 175: Execution Cycles And Pipeline Stalling
Table 8.2 Parallel-Executability 2nd Instruction Instruction O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: •...
Page 176 The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 177 Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)).
Page 178 (a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction. (b) Parallel execution: parallel-executable and no dependency 1 issue cycle EX-group ADD and LS-group MOV.L can...
Page 179 (e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result MOV.L @R1,R1 of ADD as its destination address.
Page 180 (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,R1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency 11-cycle latency FSQRT FR4 FMOV FR0,FR4 10 stall cycles = latency (11) - 1 The registers are written-back in program order.
Page 181 (h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR GBR,R2 3 stall cycles FADD DR0,DR2 MAC.W @R1+,@R2+ 5 stall cycles...
Page 182 Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data EXTS.B Rm,Rn — — — transfer EXTS.W Rm,Rn — — — instructions EXTU.B Rm,Rn — — — EXTU.W Rm,Rn —...
Page 183 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data MOV.W R0,@(disp,Rn) — — — transfer MOV.L Rm,@(disp,Rn) — — — instructions MOV.B Rm,@(R0,Rn) — — — MOV.W Rm,@(R0,Rn) —...
Page 184 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn — — — MAC.L @Rm+,@Rn+ 2/2/4/4...
Page 185 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — — — SHAD Rm,Rn —...
Page 186 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS — — — SETT —...
Page 187 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn — — — SPC,Rn —...
Page 188 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Single- FABS — — — precision FADD FRm,FRn — — — floating-point FCMP/EQ FRm,FRn — — — instructions FCMP/GT FRm,FRn —...
Page 189 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Double- FNEG — — — precision FSQRT (23, 24)/ floating-point instructions FSUB DRm,DRn (7, 8)/9 FTRC DRm,FPUL FPU system Rm,FPUL —...
Page 190 4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6.
Page 191: Power-Down Modes
Section 9 Power-Down Modes Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: •...
Page 192 Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status Power- On-chip Down Entering On-Chip Peripheral External Exiting Mode Conditions CPG Memory Modules Pins Memory Method Refreshing • Interrupt Sleep SLEEP Operating Halted Held Operating Held instruction (registers •...
Page 193: Register Configuration
9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Initial Area 7 Access Name Abbreviation Value P4 Address Address Size Standby control register STBCR H'00 H'FFC00004 H'1FC00004 Standby control register 2 STBCR2 H'00 H'FFC00010 H'1FC00010 9.1.3...
Page 194 Bit 7—Standby (STBY): Specifies a transition to standby mode. Bit 7: STBY Description Transition to sleep mode on execution of SLEEP instruction (Initial value) Transition to standby mode on execution of SLEEP instruction Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of peripheral module related pins in standby mode.
Page 195 Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is stopped when the MSTP3 bit is set to 1. Bit 3: MSTP3 Description SCIF operates (Initial value)
Page 196: Peripheral Module Pin High Impedance Control
9.2.2 Peripheral Module Pin High Impedance Control When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go to the high-impedance state in standby mode. • Relevant Pins SCI related pins MD0/SCK MD1/TXD2 MD7/TXD MD8/RTS2 CTS2...
Page 197: Standby Control Register 2 (Stbcr2)
9.2.4 Standby Control Register 2 (STBCR2) Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via the 5(6(7 pin or due to watchdog timer overflow. Bit: DSLP —...
Page 198: Sleep Mode
Sleep Mode 9.3.1 Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Page 199: Standby Mode
Standby Mode 9.5.1 Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU.
Page 200: Exit From Standby Mode
9.5.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the 5(6(7 pin. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, , or on-chip peripheral module (except interval timer) interrupt is detected, the WDT starts counting.
Page 201: Module Standby Function
Module Standby Function 9.6.1 Transition to Module Standby Function Setting the MSTP4–MSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.
Page 202: Status Pin Change Timing
STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below. The meaning of the STATUS pin settings is as follows: Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) The meaning of the clock units is as follows:...
Page 203: In Exit From Standby Mode
Manual Reset CKIO SCK2 Normal Reset Normal STATUS 0–30 Bcyc ≥ 0 Bcyc Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle. Figure 9.2 STATUS Output in Manual Reset 9.7.2 In Exit from Standby Mode...
Page 204 Standby → → → → Power-On Reset Oscillation stops Reset CKIO SCK2 Normal Standby Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When standby mode is exited by means of a power-on reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time.
Page 205: In Exit From Sleep Mode
Standby → → → → Manual Reset Oscillation stops Reset CKIO SCK2 Normal Standby Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When standby mode is exited by means of a manual reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time.
Page 206 Sleep → → → → Power-On Reset Reset CKIO SCK2 Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When sleep mode is exited by means of a power-on reset, hold low for the oscillation stabilization time. 2. Undefined Figure 9.7 STATUS Output in Sleep →...
Page 207 Sleep → → → → Manual Reset Reset CKIO SCK2 Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.8 STATUS Output in Sleep → → → → Manual Reset Sequence Rev.
Page 208: In Exit From Deep Sleep Mode
9.7.4 In Exit from Deep Sleep Mode Deep Sleep → → → → Interrupt Interrupt request CKIO Sleep STATUS Normal Normal Figure 9.9 STATUS Output in Deep Sleep → → → → Interrupt Sequence Deep Sleep → → → → Power-On Reset Reset CKIO SCK2...
Page 209 Deep Sleep → → → → Manual Reset Reset CKIO SCK2 Sleep Normal Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.11 STATUS Output in Deep Sleep → → → → Manual Reset Sequence Rev.
Page 210: Section 10 Clock Oscillation Circuits
Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control. The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed.
Page 211 The WDT has the following features • Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed. • Can be switched between watchdog timer mode and interval timer mode •...
Page 212: Overview Of Cpg
10.2 Overview of CPG 10.2.1 Block Diagram of CPG Figure 10.1 shows a block diagram of the CPG. Oscillator circuit Frequency divider 2 × 1 PLL circuit 1 × 1/2 × 6 × 1/3 CPU clock (Iø) × 1/4 cycle Icyc ×...
Page 213 The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillator by 6. Starting and stopping is controlled by a frequency control register setting.
Page 214: Cpg Pin Configuration
10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Abbreviation Function Mode control pins Input Set clock operating mode Crystal I/O pins XTAL Output Connects crystal resonator (clock input pins) EXTAL Input Connects crystal resonator, or used as...
Page 215: Clock Operating Modes
10.3 Clock Operating Modes Table 10.3 shows the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings. Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3 Clock Operating Modes External Frequency Pin Combination (vs. Input Clock) Clock Peripheral Input Clock...
Page 216: Cpg Register Description
Table 10.4 FRQCR Settings and Internal Clock Frequencies Frequency Division Ratio Clock Ratio (I:B:P)* Peripheral 1/2 Frequency 1/2 Frequency 1/2 Frequency 1/2 Frequency FRQCR (Lower Module Divider Off Divider Off Divider On Divider On 9 Bits) Clock Clock Clock PLL1 Off PLL1 On PLL1 Off PLL1 On...
Page 217 Bit: — — — — CKOEN PLL1EN PLL2EN IFC2 Initial value: — R/W: Bit: IFC1 IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0 Initial value: — — — — — — — — R/W: Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0. Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the high-impedance state.
Page 218 Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 8: IFC2 Bit 7: IFC1 Bit 6: IFC0 Description ×...
Page 219: Changing The Frequency
10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register. These methods are described below.
Page 220: Changing Bus Clock Division Ratio (When Pll Circuit 2 Is On)
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in 10.5.1. 2.
Page 221: Overview Of Watchdog Timer
10.7 Overview of Watchdog Timer 10.7.1 Block Diagram Figure 10.2 shows a block diagram of the WDT. Standby Standby Standby mode release control Frequency divider 2 ×1 clock Internal reset Frequency divider Reset request control Clock selection Clock selector Interrupt Interrupt Overflow request...
Page 222: Register Configuration
10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Initial Area 7 Name Abbreviation Value P4 Address Address Access Size Watchdog timer WTCNT R/W* H'00 H'FFC00008...
Page 223: Watchdog Timer Control/Status Register (Wtcsr)
10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the 5(6(7 pin. It retains its value in an internal reset due to WDT overflow.
Page 224 Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF Description No overflow (Initial value) WTCNT has overflowed in watchdog timer mode Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in interval timer mode.
Page 225: Notes On Register Access
10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction.
Page 226: Frequency Changing Procedure
4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt. 5. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 6.
Page 227: Using Interval Timer Mode
CL1 = CL2 = 0–33 pF R = 0Ω EXTAL XTAL SH7750 Series Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin.
Page 228 When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB, and decoupling capacitors CPB and CB, close to the pins. RCB1 VDD-PLL1 CPB1 VSS-PLL1...
Page 229: Section 11 Realtime Clock (Rtc)
Section 11 Realtime Clock (RTC) 11.1 Overview The SH7750 includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 11.1.1 Features The RTC has the following features. • Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years.
Page 230: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. RTCCLK RESET, STBY, etc 16.384 kHz RTC crystal RTC operation 32.768 kHz Prescaler oscillator control unit 128 Hz RCR1 RCR2 Counter unit Interrupt R64CNT control unit RSECCNT RMINCNT RHRCNT RDAYCNT RWKCNT...
Page 231: Pin Configuration
11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation Function RTC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillator RTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillator Clock input/clock output TCLK External clock input pin/input capture control input pin/RTC output pin...
Page 232 Table 11.2 RTC Registers Initialization Abbrevia- Power-On Manual Standby Initial Area 7 Access Name tion Reset Reset Mode Value P4 Address Address Size Month RMONCNT R/W Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8 counter Year RYRCNT R/W Counts Counts Counts Undefined H'FFC8001C H'1FC8001C 16 counter...
Page 233: Register Descriptions
11.2 Register Descriptions 11.2.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.
Page 234: Minute Counter (Rmincnt)
11.2.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 235: Day-Of-Week Counter (Rwkcnt)
11.2.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 236: Day Counter (Rdaycnt)
11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 237: Year Counter (Ryrcnt)
Bit: — — — 10-month 1-month units unit Initial value: Undefined Undefined Undefined Undefined Undefined R/W: 11.2.8 Year Counter (RYRCNT) RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter.
Page 238: Second Alarm Register (Rsecar)
11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 239: Hour Alarm Register (Rhrar)
11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 240: Day Alarm Register (Rdayar)
Bit: — — — — Day of week Initial value: Undefined Undefined Undefined R/W: Day-of-week code Day of week 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is compared with the RDAYCNT value.
Page 241: Month Alarm Register (Rmonar)
11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 242 Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again.
Page 243: Rtc Control Register 2 (Rcr2)
Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF Description Alarm registers and counter values do not match (Initial value)
Page 244 Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF Description Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF Interrupt is generated at interval specified by bits PES2–PES0...
Page 245 Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time.
Page 246: Operation
11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Set RCR2.RESET to 1 Stop clock Clear RCR2.START to 0 Reset frequency divider Set second/minute/hour/day/ In any order day-of-week/month/year Set RCR2.START to 1...
Page 247: Time Reading Procedures
The procedure for setting the time while the clock is running is shown in (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data.
Page 248 Clear RCR1.CIE to 0 Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag is not cleared) Read counter register Carry flag = 1? Read RCR1 register and check CF bit (a) Reading time without using interrupts Clear carry flag Set RCR1.CIE to 1 Enable carry interrupts...
Page 249: Alarm Function
11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Be sure to reset the flag as it may have been Clear alarm flag set during alarm time setting Set RCR1.AIE to 1 Enable alarm interrupts...
Page 250: Interrupts
11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2–...
Page 251 SH7750 Series EXTAL2 XTAL2 VDD-RTC VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value R (typ.
Page 252: Section 12 Timer Unit (Tmu)
Section 12 Timer Unit (TMU) 12.1 Overview The SH7750 includes an on-chip 32-bit timer unit (TMU) comprising three 32-bit timer channels (channels 0 to 2). 12.1.1 Features The TMU has the following features. • Auto-reload type 32-bit down-counter provided for each channel •...
Page 253: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. RESET, STBY, TUNI0 PCLK/4, 16, 64* TUNI1 TCLK RTCCLK TUNI2 TICPI2 etc. TCLK Prescaler control unit control unit To each To each channel channel TOCR TSTR Ch 0 Ch 1 Ch 2 Interrupt...
Page 254: Register Configuration
12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Com- Timer TOCR R/W Ini- Ini- Held H'00 H’FFD80000 H'1FD80000 8...
Page 255: Register Descriptions
12.2 Register Descriptions 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin.
Page 256: Timer Start Register (Tstr)
12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters (TCNT) are operated or stopped. TSTR is initialized to H'00 by a power-on or manual reset. In module standby mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (Pφ).
Page 257: Timer Constant Registers (Tcor)
12.2.3 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are three TCOR registers, one for each channel. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value. The TCOR registers are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode.
Page 258: Timer Control Registers (Tcr)
When the input clock is the on-chip RTC output clock (RTCCLK), TCNT counts even in module standby mode (that is, when the clock for the TMU is stopped). When the input clock is the external clock (TCLK) or internal clock (Pφ), TCNT contents are retained in standby mode. 12.2.5 Timer Control Registers (TCR) The TCR registers are 16-bit readable/writable registers.
Page 259 Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in channel 2 only, that indicates the occurrence of input capture.
Page 260 The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is 1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC transfer request is not generated until processing of the previous request is finished.
Page 261: Input Capture Register (Tcpr2)
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): These bits select the TCNT count clock. When the on-chip RTC output clock is selected as the count clock for a channel, that channel can operate even in module standby mode. When another clock is selected, the channel does not operate in standby mode.
Page 262: Operation
12.3 Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32- bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function.
Page 263 Operation selection Select count clock Underflow interrupt generation setting When input capture function is used Input capture interrupt generation setting Timer constant register setting Set initial timer counter value Start count Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated.
Page 264 TCNT Count Timing: • Operating on internal clock Any of five count clocks (Pφ/4, Pφ/16, Pφ/64, Pφ/256, or Pφ/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0 bits in TCR. Figure 12.4 shows the timing in this case.
Page 265: Input Capture Function
RTC output clock N + 1 N – 1 TCNT Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock 12.3.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1.
Page 266: Interrupts
TCOR value set in TCNT TCNT value on underflow TCOR H'00000000 Time TCLK TCNT value set TCPR2 TICPI2 Figure 12.7 Operation Timing when Using Input Capture Function 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used).
Page 267: Usage Notes
12.5 Usage Notes 12.5.1 Register Writes When performing a register write, timer count operation must be stopped by clearing the start bit (STR0–STR2) for the relevant channel in the timer start register (TSTR). Note that the timer start register (TSTR) can be written to, and the underflow flag (UNF) and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while the count is in progress.
Page 268: Section 13 Bus State Controller (Bsc)
The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be connected to the SH7750 Series, and also support the PCMCIA interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system.
Page 269  Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32, 16 • Synchronous DRAM interface  Row address/column address multiplexing according to synchronous DRAM capacity  Burst operation  Auto-refresh and self-refresh  Synchronous DRAM control signal timing can be controlled by register settings ...
Page 270: Block Diagram
13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. interface WCR1 Wait control unit WCR2 WCR3 Area – BCR1 control unit – BCR2 – Memory control unit RFCR RTCNT Refresh Interrupt Comparator control unit controller RTCOR RTCSR WCR: Wait control register RFCR: Refresh count register...
Page 271: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Signals Description Address bus A25–A0 Address output Data bus D63–D52, Data input/output D31–D0 When port functions are used and DDT mode is selected, input the DTR format. Otherwise, when port functions are used, D60-D52 cannot be used and should be left open.
Page 272 Table 13.1 BSC Pins (cont) Name Signals Description :(4/&$64/ Data enable 1 When setting synchronous DRAM interface: DQM1 selection signal for D15–D8 When setting DRAM interface: &$6 signal for D15–D8 When setting PCMCIA interface: write strobe signal When setting MPX interface: high-level output In other cases: write strobe signal for D15–D8 :(5/&$65/ Data enable 2...
Page 273 Table 13.1 BSC Pins (cont) Name Signals Description :(9/&$69/ Data enable 6 When setting synchronous DRAM interface: DQM6 selection signal for D55–D48 When setting DRAM interface: &$6 signal for D55–D48 When setting MPX interface: high-level output In other cases: write strobe signal for D55–D48 :(:/&$6:/ Data enable 7 When setting synchronous DRAM interface:...
Page 274 Table 13.1 BSC Pins (cont) Name Signals Description Same signal as 5'/&$66/)5$0( Read/column address strobe/ This signal is used when the 5'/&$66/)5$0( cycle frame 2 signal load is heavy. Read/write 2 RD/:55 Same signal as RD/:5 This signal is used when the RD/:5 signal load is heavy.
Page 275: Register Configuration
The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as an SH7750 Series register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing.
Page 276: Overview Of Areas
With the SH7750 Series, various kinds of memory or PC cards can be connected to the seven areas of external address as shown in table 13.3, and chip select signals (&63–&69, &(5$, &(5%) are output for each of these areas.
Page 277 Table 13.3 External Memory Space Map External Connectable Settable Bus Area Addresses Size Memory Widths Access Size H'00000000– 64 Mbytes SRAM 8, 16, 32, 64* 8, 16, 32, H'03FFFFFF bits, Burst ROM 8, 16, 32* 32 bytes 32, 64* H'04000000– 64 Mbytes SRAM 8, 16, 32, 64*...
Page 278 Figure 13.3 External Memory Space Allocation Memory Bus Width: In the SH7750 Series, the memory bus width can be set independently for each space. For area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset, using external pins.
Page 279: Pcmcia Support
The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used. 13.1.6 PCMCIA Support The SH7750 Series supports PCMCIA compliant interface specifications for external memory space areas 5 and 6. The interfaces supported are the IC memory card interface and I/O card interface stipulated in JEIDA specifications version 4.2 (PCMCIA2.1).
Page 280 Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Ground Ground — I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data...
Page 281 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data ,2,649 ,2,649...
Page 282 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Reserved Reserved — RESET Reset RESET Reset Output from port :$,7 :$,7 5'< Wait request Wait request ,13$&.
Page 283: Register Descriptions
13.2 Register Descriptions 13.2.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 284 Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin (MD5) in a power-on reset. The endian mode of all spaces is determined by this bit. ENDIAN is a read-only bit. Bit 31: ENDIAN Description In a power-on reset, the endian setting external pin (MD5) is low, designating big-endian mode for the SH7750 In a power-on reset, the endian setting external pin (MD5) is high, designating little-endian mode for the SH7750...
Page 285 Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor status for control input pins (NMI, ,5/3–,5/6, %5(4, MD6/,2,649, 5'<). IPUP is initialized by a power-on reset. Bit 25: IPUP Description Pull-up resistor is on for control input pins (NMI, ,5/3–,5/6, %5(4, MD6/,2,649, 5'<) (Initial value) Pull-up resistor is off for control input pins (NMI, ,5/3–,5/6, %5(4,...
Page 286 Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted. BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup. Bit 19: BREQEN Description External requests are not accepted (Initial value) External requests are accepted...
Page 287 Bit 14—High Impedance Control (HIZCNT): Specifies the state of the 5$6 and &$6 signals in standby mode and when the bus is released. Bit 14: HIZCNT Description The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals go to high-impedance (High-Z) in standby mode and when the bus is released (Initial value) The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals...
Page 288 Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0...
Page 289 Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 Bit 6: A6BST1 Bit 5: A6BST0...
Page 290 Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description Areas 2 and 3 are SRAM interface or MPX interface*...
Page 291: Bus Control Register 2 (Bcr2)
13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 292: Wait Control Register 1 (Wcr1)
In the SH7750 Series, the number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision.
Page 293 Bit: Bit name: — DMAIW2 DMAIW1 DMAIW0 — A6IW2 A6IW1 A6IW0 Initial value: R/W: Bit: Bit name: — A5IW2 A5IW1 A5IW0 — A4IW2 A4IW1 A4IW0 Initial value: R/W: Bit: Bit name: — A3IW2 A3IW1 A3IW0 — A2IW2 A2IW1 A2IW0 Initial value: R/W: Bit: Bit name:...
Page 294: Wait Control Register 2 (Wcr2)
DMAIW2/AnIW2 DMAIW1/AnIW1 DMAIW0/AnIW0 Inserted Idle Cycles (Initial value) • Idle Insertion between Accesses Following Cycle Same Different Same Area Different Area Area Area Read Write Read Write Preceding Address Address Cycle CPU DMA CPU DMA CPU DMA CPU DMA Output Output Read M (1)
Page 295 WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: Bit name: A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1 Initial value: R/W: Bit: Bit name: A5W0 A5B2 A5B1 A5B0 A4W2...
Page 296 Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from Second Data 5'<...
Page 297 Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from 5'< Pin 5'<...
Page 298 Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait states to be inserted for area 3. External wait input is only enabled when SRAM interface is used, and is ignored when DRAM or synchronous DRAM is used. •...
Page 299 Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states to be inserted for area 2. External wait input is only enabled when normal memory is used, and is ignored when DRAM or synchronous DRAM is used. •...
Page 300 Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states to be inserted for area 1. Description 5'< 5'< Pin 5'< 5'< Bit 8: A1W2 Bit 7: A1W1 Bit 6: A1W0 Inserted Wait States Ignored Enabled Enabled...
Page 301 Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the burst pitch to in burst ROM interface setting. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from 5'< Pin 5'< 5'< 5'< Bit 2: A0B2 Bit 1: A0B1 Bit 0: A0B0 Second Data Access Onward Ignored...
Page 302: Wait Control Register 3 (Wcr3)
13.2.5 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. This enables low-speed memory to be connected without using external circuitry.
Page 303: Memory Control Register (Mcr)
Valid only for SRAM interface and burst ROM interface: Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Bit 4n + 2: AnS0 Waits Inserted in Setup (Initial value)
Page 304 Bit: Bit name: RASD MRSET TRC2 TRC1 TRC0 — — — Initial value: R/W: Bit: Bit name: TCAS — TPC2 TPC1 TPC0 — RCD1 RCD0 Initial value: R/W: Bit: Bit name: TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 Initial value: R/W: Bit: Bit name: AMXEXT AMX2...
Page 305 Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0) (Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both enabled) RAS Precharge Interval Bit 29: TRC2 Bit 28: TRC1 Bit 27: TRC0 Immediately after Refresh (Initial value) Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written with 0.
Page 306 RAS Precharge Interval Bit 21: TPC2 Bit 20: TPC1 Bit 19: TPC0 DRAM Synchronous DRAM 1* (Initial value) Note: * Inhibited in RAS down mode. Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits set the 5$6-&$6 assertion delay time.
Page 307 Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0 Write Precharge ACT Delay Time 1 (Initial value) Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Note: * Inhibited in RAS down mode. Bits 12 to 10—CAS-Before-RAS Refresh 5$6 5$6 Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the 5$6 assertion period in CAS-before-RAS refreshing.
Page 308 EDOMODE 8/16/32/64-Bit Transfer 32-Byte Transfer Single Single Setting prohibited Setting prohibited Single/fast page* Fast page Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus. Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM.
Page 309 (16M: 256k × 32 bits × 2) × 1 a[20]* Notes: 1. a[*]: External address 2. Setting prohibited in the SH7750 Series. 3. Setting prohibited in the SH7750. 4. Can only be set in the SH7750S. Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is performed for DRAM and synchronous DRAM.
Page 310: Pcmcia Control Register (Pcr)
Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS- before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR.
Page 311 Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA access TC bit is cleared to 0. Bit 15: A5PCW1 Bit 14: A5PCW0 Waits Inserted...
Page 312 2(/:( :( Assertion Delay (A6TED2–A6TED0): These bits set the delay Bits 8 to 6—Address-2( time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA access TC bit is set to 1. Bit 8: A6TED2 Bit 7: A6TED1 Bit 6: A6TED0...
Page 313: Synchronous Dram Mode Register (Sdmr)
DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of the SH7750 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7750 Rev. 4.0, 04/00, page 302 of 850...
Page 314 Series, the value actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right. For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written to the SDMR register.
Page 315: Refresh Timer Control/Status Register (Rtscr)
13.2.9 Refresh Timer Control/Status Register (RTSCR) The refresh timer control/status register (RTSCR) is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated. RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 316 Bits 5 to 3—Clock Select Bits (CKS2–CKS0): These bits select the input clock for RTCNT. The base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO by the specified factor. Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description...
Page 317: Refresh Timer Counter (Rtcnt)
Bit 0—Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value exceeds the value specified by LMTS, the OVF flag is set. Bit 0: LMTS Description Count limit is 1024...
Page 318: Refresh Count Register (Rfcr)
RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: Bit name: — — — — — — — — Initial value: R/W: — —...
Page 319: 13.2.13 Notes On Accessing Refresh Control Registers
13.2.13 Notes on Accessing Refresh Control Registers When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The following procedures should be used for read/write operations.
Page 320: Operation
13.3.1 Endian/Access Size and Data Alignment The SH7750 Series supports both big-endian mode, in which the most significant byte (MSByte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (LSByte) is at the 0 address end.
Page 321 Table 13.6 (1) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte Data — — — — — — — 7–0 8n+1 — Data — — —...
Page 322 Table 13.6 (2) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Strobe Signals :(:, :(9, :(8, :(7, :(6, :(5, :(4, :(3, &$6:, &$6: &$69 &$69, &$68, &$68 &$67 &$67, &$66, &$66 &$65, &$65 &$64 &$64, &$63 &$63, &$6: &$6: &$69 &$69 &$68 &$68...
Page 323 Table 13.7 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66, &$66 &$65 &$65, &$64 &$64, &$63 &$63, &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 324 Table 13.8 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66 &$66, &$65, &$65 &$64, &$64 &$63, &$63 &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 325 Table 13.9 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66, &$66 &$65 &$65, &$64 &$64, &$63 &$63, &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 326 Table 13.10 (1) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte — — — — — — — Data 7–0 8n+1 — — — — —...
Page 327 Table 13.10 (2) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Strobe Signals :(:, :(9, :(8, :(7, :(6, :(5, :(4, :(3, &$6: &$6:, &$69, &$69 &$68 &$68, &$67, &$67 &$66, &$66 &$65 &$65, &$64, &$64 &$63, &$63 &$6: &$6: &$69 &$69 &$68 &$68...
Page 328 Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66, &$66 &$65 &$65, &$64 &$64, &$63 &$63, &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3...
Page 329 Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66 &$66, &$65, &$65 &$64 &$64, &$63, &$63 &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 330 Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66 &$66, &$65, &$65 &$64, &$64 &$63, &$63 &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 331: Areas
13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins MD4 and MD3.
Page 332 interface is set, select 32 or 64 bits with the SZ bits in the MCR register. When DRAM is connected to area 2, select a bus width of 16 or 32 bits with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5.
Page 333 The read/write strobe signal address and &6 setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3 register. When synchronous DRAM interface is set, the 5$6 and &$6 signals, RD/:5 signal, and byte control signals DQM0 to DQM7 are asserted, and address multiplexing is performed.
Page 334 as 2(, and the :(4, :(5, :(6, and :(: signals, which can be used as :(, ,&,25', ,&,2:5, and 5(*, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register.
Page 335: Basic Interface
13.3.3 Basic Interface Basic Timing: The basic interface of the SH7750 Series uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.5 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The %6 signal is asserted for one cycle to indicate the start of a bus cycle.
Page 336 CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Single address DMA Dual address DMA Figure 13.5 Basic Timing of Basic Interface Rev. 4.0, 04/00, page 325 of 850...
Page 337 Figures 13.6, 13.7, 13.8, and 13.9 show examples of connection to 64-, 32-, 16-, and 8-bit data width SRAM. × 128K 8-bit SH7750 Series SRAM A19–A3 A16–A0 D63–D56 I/O7–I/O0 A16–A0 D55–D48 I/O7–I/O0 A16–A0 D47–D40 I/O7–I/O0 A16–A0 D39–D32 I/O7–I/O0 A16–A0 D31–D24 I/O7–I/O0...
Page 338 128K × 8-bit SH7750 Series SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 13.7 Example of 32-Bit Data Width SRAM Connection Rev. 4.0, 04/00, page 327 of 850...
Page 339 128K × 8-bit SH7750 Series SRAM I/O7 I/O0 I/O7 I/O0 Figure 13.8 Example of 16-Bit Data Width SRAM Connection Rev. 4.0, 04/00, page 328 of 850...
Page 340 128K × 8-bit SH7750 Series SRAM I/O7 I/O0 Figure 13.9 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification.
Page 341 CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Figure 13.10 Basic Interface Wait Timing (Software Wait Only) Rev. 4.0, 04/00, page 330 of 850...
Page 342 When software wait insertion is specified by WCR2, the external wait input 5'< signal is also sampled. 5'< signal sampling is shown in figure 13.11. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the 5'<...
Page 343: Dram Interface
13.3.4 DRAM Interface Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to 100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The DRAM interface function can then be used to connect DRAM to the SH7750. 16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2–0 are set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2–0 are set to 101.
Page 344 1M × 16-bit SH7750 Series DRAM A12–A3 A9–A0 I/O15–I/O0 D63–D48 A9–A0 D47–D32 I/O15–I/O0 A9–A0 D31–D16 I/O15–I/O0 A9–A0 D15–D0 I/O15–I/O0 Figure 13.12 Example of DRAM Connection (64-Bit Data Width, Area 3) Rev. 4.0, 04/00, page 333 of 850...
Page 345 256K × 16-bit SH7750 Series DRAM I/O15 I/O0 I/O15 I/O0 Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3) Rev. 4.0, 04/00, page 334 of 850...
Page 346 256K × 16-bit SH7750 Series DRAM Area 3 I/O15 I/O0 Area 2 I/O15 I/O0 Figure 13.14 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) Rev. 4.0, 04/00, page 335 of 850...
Page 347 DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to the SH7750 Series without using an external address multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM.
Page 348 Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.15. Tpc is the precharge cycle, Tr the 5$6 assert cycle, Tc1 the &$6 assert cycle, and Tc2 the read data latch cycle. CKIO A25–A0 Column...
Page 349 Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.16.
Page 350 Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access.
Page 351 EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only while the &$6 signal is asserted in a data read cycle, an EDO (extended data out) mode is also provided in which, once the &$6 signal is asserted while the 5$6 signal is asserted, even if the &$6 signal is negated, data is output to the data bus until the &$6 signal is next asserted.
Page 352 (SA: IO ← memory) Figure 13.19 Burst Access Timing in DRAM EDO Mode RAS Down Mode: The SH7750 Series has an address comparator for detecting row address matches in burst mode. By using this address comparator, and also setting RAS down mode specification bit RASD to 1, it is possible to select RAS down mode, in which 5$6 remains asserted after the end of an access.
Page 353 CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Figure 13.20 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, Anw = 0) Rev. 4.0, 04/00, page 342 of 850...
Page 354 Tnop CKIO A25–A0 End of RAS down mode D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Figure 13.20 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0) Rev.
Page 355 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.20 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, Anw = 0) Rev. 4.0, 04/00, page 344 of 850...
Page 356 CKIO A25–A0 End of RAS down mode D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.20 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, Anw = 0) Rev. 4.0, 04/00, page 345 of 850...
Page 357 RTCOR value, and if the two values are the same, a refresh request is generated and the %$&. pin goes high. If the SH7750 Series’ external bus can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted.
Page 358 Figure 13.22 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) • Self-Refresh The self-refreshing supported by the SH7750 Series is shown in figure 13.23. After the self-refresh is cleared, the refresh controller immediately generates a refresh request.
Page 359 1. Normally, set the refresh counter count cycle to the optimum value for the L version (e.g. 1024 cycles/128 ms). 2. When a transition is made to self-refreshing: a. Provide an interrupt handler to restore the refresh counter count value to the optimum value for the L version (e.g.
Page 360 SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series. TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 D63–D0 Figure 13.23 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 µs or 200 µs) during which no access can be performed be provided, followed by at...
Page 361: Synchronous Dram Interface
DRAM space. With the SH7750 Series, burst read/burst write mode is supported as the synchronous DRAM operating mode. The data bus width is 32 or 64 bits, and the SZ size bits in MCR must be set to 00 or 11.
Page 362 512K × 16-bit × 2-bank SH7750 Series synchronous DRAM A12–A3 A9–A0 CKIO D63–D48 I/O15–I/O0 DQM7 DQMU DQM6 DQML A9–A0 I/O15–I/O0 D47–D32 DQMU DQM5 DQML DQM4 A9–A0 D31–D16 I/O15–I/O0 DQM3 DQMU DQM2 DQML A9–A0 D15–D0 I/O15–I/O0 DQM1 DQMU DQM0 DQML Figure 13.24 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3)
Page 363 The address signals output at A25–A18, A1, and A0 are undefined. When A0, the LSB of the synchronous DRAM address, is connected to the SH7750 Series, with a 32-bit bus width it makes a longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of the SH7750, then connect pin A1 to pin A3.
Page 364 DRAM; no new access command can be issued to the same bank during this cycle. In the SH7750 Series, the number of Tpc cycles is determined by the specification of bits TPC2– TPC0 in MCR, and commands are not issued for the same synchronous DRAM during this interval.
Page 365 independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.26 Basic Timing for Synchronous DRAM Burst Read In a synchronous DRAM cycle, the %6 signal is asserted for one cycle at the start of the data transfer cycle corresponding to the READ or READA command.
Page 366 To prevent data collisions, after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the SH7750 Series waits for the end of the synchronous DRAM operation. The %6 signal is asserted only in Td1.
Page 367 Burst Write: The timing chart for a burst write is shown in figure 13.28. In the SH7750, a burst write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write operation, the WRIT command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output and, 4 cycles later, the WRITA command is issued.
Page 368 Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. As the SH7750 Series supports burst read/burst write operations for synchronous DRAM, there are empty cycles in a single write operation.
Page 369 Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Figure 13.29 Basic Timing for Synchronous DRAM Single Write Rev. 4.0, 04/00, page 358 of 850...
Page 370 RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
Page 371 that in figure 13.31 or 13.34. In RAS down mode, too, a PRE command is issued before a refresh cycle or before bus release due to bus arbitration. Tc3 Tc4/Td1 Td2 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.30 Burst Read Timing Rev.
Page 372 Tc3 Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.31 Burst Read Timing (RAS Down, Same Row Address) Rev. 4.0, 04/00, page 361 of 850...
Page 373 Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.32 Burst Read Timing (RAS Down, Different Row Addresses) Rev. 4.0, 04/00, page 362 of 850...
Page 374 Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Figure 13.33 Burst Write Timing Rev. 4.0, 04/00, page 363 of 850...
Page 375 Tncp* Tnop* Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Notes: 1. Tncp: DACK output start cycle (inserted only in the case of DACK output) 2. Tnop: Dummy cycle (always inserted) Figure 13.34 Burst Write Timing (Same Row Address) Rev.
Page 376 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Figure 13.35 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM.
Page 377 addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACT command, depending on the bank and row address, but since the write data is output at the same time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that one or two empty cycles occur automatically on the data bus.
Page 378 Tc1_A Tc1_B CKIO Bank Precharge-sel Address DQMn D63–D0 (read) Figure 13.36 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR.
Page 379 First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by bits TRAS2–TRAS0 in MCR plus the number of cycles specified by bits TRC2–TRC0 in MCR. The TRAS2– TRAS0 and TRC2–TRC0 bits must be set so as to satisfy the synchronous DRAM refresh cycle time specification (active/active command delay time).
Page 380 TRr1 TRr2 TRr3 TRr4 TRrw TRr5 CKIO DQMn D63–D0 Figure 13.38 Synchronous DRAM Auto-Refresh Timing • Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1.
Page 381 When a refresh request is generated, the %$&. pin is negated (driven high). Therefore, normal refreshing can be performed by having the %$&. pin monitored by a bus master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series.
Page 382 Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the 5$6, &$6, and RD/:5 signals.
Page 383 Synchronous DRAM mode register setting should be executed once only after power-on and before synchronous DRAM access, and no subsequent changes should be made. TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address D31–D0 (High) Figure 13.40 (1) Synchronous DRAM Mode Write Timing Rev.
Page 384 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address D31–D0 (High) Figure 13.40 (2) Synchronous DRAM Mode Write Timing Rev. 4.0, 04/00, page 373 of 850...
Page 385: Burst Rom Interface
13.3.6 Burst ROM Interface Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a non- zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 13.41.
Page 386 CKIO A25–A5 A4–A0 D63–D0 (read) DACKn (SA: IO ← memory) Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 13.41 Burst ROM Basic Access Timing Rev. 4.0, 04/00, page 375 of 850...
Page 387 CKIO A25–A5 A4–A0 D63–D0 (read) DACKn (SA: IO ← memory) Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 13.42 Burst ROM Wait Access Timing Rev. 4.0, 04/00, page 376 of 850...
Page 388: Pcmcia Interface
13.3.7 PCMCIA Interface In the SH7750 Series (SH7750 and SH7750S), setting the A56PCM bit in BCR1 to 1 makes the bus interface for external space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1).
Page 389 to A6TEH0 in the PCMCIA control register (PCR), are selected. For the method of setting bits SA2 to SA0 and bit TC, see the MMU section. In the SH7750S, the PCMCIA interface can be accessed even when the MMU is not used. When the MMU is off, access is always performed by means of bits SA2 to SA0 and bit TC in the page table entry assistance register (PTEA).
Page 390 Table 13.17 Relationship between Address and CE When Using PCMCIA Interface Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Read Even Don’t — Invalid Read data care Don’t — Invalid Read data care Even Don’t...
Page 391 Table 13.17 Relationship between Address and CE When Using PCMCIA Interface (cont) Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Dynamic Read Even — Invalid Read data — Read data Invalid sizing* Even —...
Page 392 A25–A0 A25–A0 D15–D0 D7–D0 D15–D0 PC card D15–D8 (memory I/O) SH7750 Series Card detection CD1, CD2 circuit Output A25–A0 Port D7–D0 D15–D0 D15–D8 PC card (memory I/O) Card CD1, CD2 detection circuit Figure 13.44 Example of PCMCIA Interface Rev. 4.0, 04/00, page 381 of 850...
Page 393 Memory Card Interface Basic Timing: Figure 13.45 shows the basic timing for the PCMCIA IC memory card interface, and figure 13.46 shows the PCMCIA memory bus wait timing. Tpcm1 Tpcm2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.45 Basic Timing for PCMCIA Memory Card Interface Rev.
Page 394 Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.46 Wait Timing for PCMCIA Memory Card Interface Rev. 4.0, 04/00, page 383 of 850...
Page 395 Common memory (64 MB) Physical Access address space by CS5 wait Physical I/O controller addresses 1 kB IO 1 Virtual Access page address space by CS6 wait IO 1 controller Common IO 2 memory 1 Card 1 Common memory 2 on CS5 IO 2 Attribute memory...
Page 396 Tpci1 Tpci2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.48 Basic Timing for PCMCIA I/O Card Interface Rev. 4.0, 04/00, page 385 of 850...
Page 397 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.49 Wait Timing for PCMCIA I/O Card Interface Rev. 4.0, 04/00, page 386 of 850...
Page 398 Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w CKIO A25–A1 CExx REG (WE7) RD/WR IORD (WE2) (read) D15–D0 (read) IOWR (WE3) (write) D15–D0 (write) IOIS16 DACKn (DA) Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.
Page 399: Mpx Interface
Access Size Byte Word Longword Quadword 32-byte burst X: Don’t care SH7750 Series MPX device CKIO D63–D0 I/O63–I/O0 Figure 13.51 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 or 64 bits should be specified in BCR2.
Page 400 For wait control, waits specified by WCR2 and wait insertion by means of the 5'< pin can be used. In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to Tmd1w Tmd1 CKIO D63–D0 DACKn (DA)
Page 401 Tmd1w Tmd1w Tmd1 CKIO D63–D0 DACKn (DA) Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) Rev. 4.0, 04/00, page 390 of 850...
Page 402 Tmd1 CKIO D63–D0 DACKn (DA) Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits) Rev. 4.0, 04/00, page 391 of 850...
Page 403 Tmd1w Tmd1w Tmd1 CKIO D63–D0 DACKn (DA) Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) Rev. 4.0, 04/00, page 392 of 850...
Page 404 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 393 of 850...
Page 405 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 394 of 850...
Page 406 Tmd1 Tmd2 Tmd3 Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 395 of 850...
Page 407 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 396 of 850...
Page 408 Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.60 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 397 of 850...
Page 409 Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.61 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 398 of 850...
Page 410 Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.62 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 399 of 850...
Page 411 Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.63 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 400 of 850...
Page 412 Figure 13.64 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 401 of 850...
Page 413 Figure 13.65 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 402 of 850...
Page 414 Figure 13.66 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 403 of 850...
Page 415 Figure 13.67 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 404 of 850...
Page 416: Byte Control Sram
13.3.9 Byte Control SRAM The byte control SRAM interface is a memory interface that outputs a byte select strobe (:(Q) in both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has an upper byte select strobe and lower byte select strobe function such as UB and LB.
Page 417 64K × 16-bit SH7750 Series SRAM A18–A3 A15–A0 I/O15–I/O0 D63–D48 A15–A0 D47–D32 I/O15–I/O0 A15–A0 D31–D16 I/O15–I/O0 A15–A0 D15–D0 I/O15–I/O0 Figure 13.68 Example of 64-Bit Data Width Byte Control SRAM Rev. 4.0, 04/00, page 406 of 850...
Page 418 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Figure 13.69 Byte Control SRAM Basic Read Cycle (No Wait) Rev. 4.0, 04/00, page 407 of 850...
Page 419 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev. 4.0, 04/00, page 408 of 850...
Page 420 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev. 4.0, 04/00, page 409 of 850...
Page 421: 13.3.10 Waits Between Access Cycles
13.2.3, Wait Control Register (WCR1). When the SH7750 Series performs consecutive write cycles, the data transfer direction is fixed (from the SH7750 Series to other memory) and there is no problem. With read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed.
Page 422: 13.3.11 Bus Arbitration
Figure 13.72 Waits between Access Cycles 13.3.11 Bus Arbitration The SH7750 Series is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. Also provided is a bus arbitration function to support the connection of two processors.
Page 423 Bus transfer is executed between bus cycles. When the bus release request signal (%5(4) is asserted, the SH7750 Series releases the bus as soon as the currently executing bus cycle ends, and outputs the bus use permission signal (%$&.).
Page 424 As the CPU in the SH7750 Series is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the SH7750 Series. When writing from the CPU, an external write cycle is generated when write-through has been set for the cache in the SH7750 Series, or when an access is made to a cache-off area.
Page 425 CKIO Asserted for at least 2 cyc Negated within 2 cyc A25–A0 D63–D0 (write) Master mode device access Must be asserted for Must be negated within 2 cyc at least 2 cyc A25–A0 D63–D0 (write) Slave mode device access Master access Slave access Master access Figure 13.73 Arbitration Sequence...
Page 426: 13.3.12 Master Mode
%$&. signal is negated even while the %5(4 signal is asserted to request the slave to relinquish the bus. When the SH7750 Series is used in master mode, consecutive bus accesses may be attempted to reduce the overhead due to arbitration in the case of a slave designed independently...
Page 427: 13.3.13 Slave Mode
by the user. When connecting a slave for which the total duration of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the %$&. signal is detected. 13.3.13 Slave Mode In slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence.
Page 428 Partial-sharing master mode is designed for use in conjunction with a master mode chip. The partial-sharing master can access a device on the master side via area 2, but the master cannot access a device on the partial-sharing master side. An address and control signal buffer and a data buffer must be located between the partial-sharing master and the master, and controlled by a buffer control circuit.
Page 429: 13.3.15 Cooperation Between Master And Slave
2, while the master performs initialization of the memory connected to it. If the SH7750 Series is specified as the master in a power-on reset, it will not accept bus requests from the slave until the %5(4 enable bit (BCR1.BREQEN) is set to 1.
Page 430: Section 14 Direct Memory Access Controller (Dmac)
14.1 Overview The SH7750 Series includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (DMA transfer end notification), external memories, memory- mapped external devices, and on-chip peripheral modules (except the DMAC, BSC, and UBC).
Page 431 • Choice of bus mode: Cycle steal mode or burst mode • Two types of DMAC channel priority ranking:  Fixed priority mode: Channel priorities are permanently fixed.  Round robin mode: Sets the lowest priority for the channel for which an execution request was last accepted.
Page 432: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of the DMAC. DMAC module Count SARn control Register