Page 1 Hitachi SuperH™ RISC engine SH7750 Series SH7750, SH7750S Hardware Manual ADE-602-124C Rev. 4.0 4/21/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 Preface The SH-4 (SH7750 Series (SH7750, SH7750S)) has been developed as the top-end model in the SuperH™ RISC engine family, featuring a 128-bit graphic engine for multimedia applications and 360 MIPS performance. The SH7750 Series CPU has a RISC type instruction set, and features upward-compatibility at the object code level with SH-1, SH-2, SH-3, and SH-3E microcomputers.
Page 4 Revisions and Additions in this Edition Page Item Revisions (See Manual for Details) 1.1 SH7750 Features 167 MHz and 128 MHz operating Table 1.1 frequency versions added 5.3.1 Exception Handling Flow • R15 added to description • Save general register 15 (SGR) added to description •...
Page 5 Page Item Revision (See Manual for Details) 386 to 391 13.3.8 MPX Interface MPX interface timing conditions amended Figures 13.52 to 13.59 687, 688 22.2.2 Pin Functions (208-Pin QFP) Table amended Table 22.2 Pin Functions Pin nos. 137, 139, 141, 145 Data amended to data/port Section 23 Electronical Characteristics HD6417750BP200H,...
Page 6: Table Of Contents
Contents Section 1 Overview ......................SH7750 Series Features ....................Block Diagram ........................Section 2 Programming Model ..................Data Formats........................Register Configuration...................... 10 2.2.1 Privileged Mode and Banks ................. 10 2.2.2 General Registers ....................13 2.2.3 Floating-Point Registers..................15 2.2.4 Control Registers ....................17 2.2.5...
Page 7 3.5.2 MMU Software Management ................45 3.5.3 MMU Instruction (LDTLB)................. 45 3.5.4 Hardware ITLB Miss Handling ................46 3.5.5 Avoiding Synonym Problems ................47 MMU Exceptions......................48 3.6.1 Instruction TLB Multiple Hit Exception.............. 48 3.6.2 Instruction TLB Miss Exception................49 3.6.3 Instruction TLB Protection Violation Exception ..........
Page 8 4.5.4 OC Data Array ..................... 78 Store Queues ........................79 4.6.1 SQ Configuration....................79 4.6.2 SQ Writes......................79 4.6.3 Transfer to External Memory................79 4.6.4 SQ Protection....................... 81 Section 5 Exceptions ......................83 Overview........................... 83 5.1.1 Features........................ 83 5.1.2 Register Configuration..................83 Register Descriptions ......................
Page 9 6.6.2 Pair Single-Precision Data Transfer..............128 Section 7 Instruction Set ....................129 Execution Environment ....................129 Addressing Modes ......................131 Instruction Set ........................135 Section 8 Pipelining ......................149 Pipelines..........................149 Parallel-Executability......................156 Execution Cycles and Pipeline Stalling ................160 Section 9 Power-Down Modes ..................
Page 10 10.1.1 Features........................ 197 10.2 Overview of CPG......................199 10.2.1 Block Diagram of CPG..................199 10.2.2 CPG Pin Configuration ..................201 10.2.3 CPG Register Configuration ................201 10.3 Clock Operating Modes ....................202 10.4 CPG Register Description ....................203 10.4.1 Frequency Control Register (FRQCR)..............203 10.5 Changing the Frequency ....................
Page 11 11.2.8 Year Counter (RYRCNT) ..................225 11.2.9 Second Alarm Register (RSECAR) ..............226 11.2.10 Minute Alarm Register (RMINAR) ..............226 11.2.11 Hour Alarm Register (RHRAR) ................227 11.2.12 Day-of-Week Alarm Register (RWKAR)............227 11.2.13 Day Alarm Register (RDAYAR) ................. 228 11.2.14 Month Alarm Register (RMONAR) ..............
Page 12 13.1.1 Features........................ 257 13.1.2 Block Diagram..................... 259 13.1.3 Pin Configuration....................260 13.1.4 Register Configuration..................264 13.1.5 Overview of Areas ....................265 13.1.6 PCMCIA Support ....................268 13.2 Register Descriptions ......................272 13.2.1 Bus Control Register 1 (BCR1) ................272 13.2.2 Bus Control Register 2 (BCR2) ................280 13.2.3 Wait Control Register 1 (WCR1).................
Page 13 14.1.4 Register Configuration..................423 14.2 Register Descriptions ......................425 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......... 425 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)........426 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......427 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)........428 14.2.5 DMA Operation Register (DMAOR)..............
Page 14 15.3.3 Multiprocessor Communication Function ............543 15.3.4 Operation in Synchronous Mode ................. 551 15.4 SCI Interrupt Sources and DMAC ..................560 15.5 Usage Notes ........................561 Section 16 Serial Communication Interface with FIFO (SCIF) ......565 16.1 Overview........................... 565 16.1.1 Features........................ 565 16.1.2 Block Diagram.....................
Page 15 17.3.2 Pin Connections ....................619 17.3.3 Data Format ......................620 17.3.4 Register Settings ....................621 17.3.5 Clock........................623 17.3.6 Data Transfer Operations..................626 17.4 Usage Notes ........................633 Section 18 I/O Ports ......................639 18.1 Overview........................... 639 18.1.1 Features........................ 639 18.1.2 Block Diagrams ....................
Page 16 20.6.1 Transition to User Break Controller Stopped State..........701 20.6.2 Cancelling the User Break Controller Stopped State ........... 701 20.6.3 Examples of Stopping and Restarting the User Break Controller......702 Section 21 Hitachi User Debug Interface (H-UDI) ........... 703 21.1 Overview........................... 703 21.1.1 Features........................
Page 17 21.2.3 Bypass Register (SDBPR) ................... 708 21.3 Operation .......................... 709 21.3.1 TAP Control......................709 21.3.2 H-UDI Reset ......................710 21.3.3 H-UDI Interrupt ....................710 21.3.4 Bypass........................710 21.4 Usage Notes ........................711 Section 22 Pin Description ....................713 22.1 Pin Arrangement ....................... 713 22.2 Pin Functions ........................
Page 18: Overview
MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The SH7750 Series has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
Page 19 Table 1.1 SH7750 Series Features (cont) Item Features • Original Hitachi SH architecture • 32-bit internal data bus • General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers •...
Page 20 Table 1.1 SH7750 Series Features (cont) Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero •...
Page 21 Table 1.1 SH7750 Series Features (cont) Item Features • Clock pulse Choice of main clock: 1/2, 1, 3, or 6 times EXTAL generator (CPG) • Clock modes:  CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock: maximum 200 MHz ...
Page 22 Table 1.1 SH7750 Series Features (cont) Item Features • Cache memory Instruction cache (IC)  8 kbytes, direct mapping  256 entries, 32-byte block length  Normal mode (8-kbyte cache)  Index mode • Operand cache (OC)  16 kbytes, direct mapping ...
Page 23 Table 1.1 SH7750 Series Features (cont) Item Features • Bus state Supports external memory access controller (BSC)  64/32/16/8-bit external data bus • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: ...
Page 24 Table 1.1 SH7750 Series Features (cont) Item Features • Serial Two full-duplex communication channels (SCI, SCIF) communication • Channel 1 (SCI): interface  Choice of asynchronous mode or synchronous mode (SCI, SCIF)  Supports smart card interface • Channel 2 (SCIF): ...
Page 25: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram of the SH7750 Series. Lower 32-bit data Lower 32-bit data I cache O cache ITLB UTLB (8 kB) (16 kB) INTC DMAC (SCIF) External bus interface 26-bit 64-bit address data BSC:...
Page 26: Programming Model
Section 2 Programming Model Data Formats The data formats handled by the SH7750 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 27: Register Configuration
Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH7750 has two processor modes, user mode and privileged mode. The SH7750 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processor modes.
Page 28: General Registers
Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.
Page 29 R0 _ BANK0* R0 _ BANK1* R0 _ BANK0* R1 _ BANK0* R1 _ BANK1* R1 _ BANK0* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK1* R3 _ BANK0* R4 _ BANK0* R4 _ BANK0* R4 _ BANK1* R5 _ BANK0* R5 _ BANK0*...
Page 30 R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7750 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
Page 31 SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...
Page 32: Floating-Point Registers
2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Page 33 • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10...
Page 34: Control Registers
Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 16 15 14 —...
Page 35: System Registers
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 36 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 37: Memory-Mapped Registers
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 38: Data Format In Registers
Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Data Format in Registers Register operands are always longwords (32 bits).
Page 39: Processor States
Little endian Figure 2.5 Data Formats In Memory Note: The SH7750 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed.
Page 40 Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 9, Power-Down Modes.
Page 41: Processor Modes
Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1.
Page 42: Memory Management Unit (Mmu)
(translation lookaside buffer: TLB). The SH7750 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte).
Page 43 (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7750 Series is referred to as virtual address space, and the address space in physical memory as physical address space.
Page 44 Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev. 4.0, 04/00, page 27 of 850...
Page 45: Register Configuration
3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Name tion Value* Address* Address* Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register Page table entry low PTEL Undefined H'FF00 0004 H'1F00 0004 32...
Page 46: Register Descriptions
Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.
Page 47 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware.
Page 48 instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software.
Page 49: Memory Space
3.3.1 Physical Memory Space The SH7750 Series supports a 32-bit physical memory space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical memory space. The physical memory space is divided into a number of areas, as shown in figure 3.3.
Page 50: External Memory Space
P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4.
Page 51 H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000 Operand cache data array H'F600 0000...
Page 52 3.3.2 External Memory Space The SH7750 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC).
Page 53: Virtual Memory Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH7750 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1- Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.
Page 54: On-Chip Ram Space
3.3.4 On-Chip RAM Space In the SH7750 Series, half (8 kbytes) of the instruction cache (16 kbytes) can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area.
Page 55: Single Virtual Memory Mode And Multiple Virtual Memory Mode
address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either...
Page 56 Entry 0 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 1 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 2 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 63 ASID [7:0] VPN [31:10] V...
Page 57 • ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed.
Page 58 • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1.
Page 59: Instruction Tlb (Itlb) Configuration
3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries.
Page 60 Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match...
Page 61 Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match VPNs match...
Page 62: Mmu Functions
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7750 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.
Page 63: Hardware Itlb Miss Handling
3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7750 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB.
Page 64: Avoiding Synonym Problems
This problem does not occur with the instruction TLB or instruction cache . In the SH7750 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4- kbyte page, are subject to address translation.
Page 65: Mmu Exceptions
MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 66: Instruction Tlb Miss Exception
3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below.
Page 67: Instruction Tlb Protection Violation Exception
3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.
Page 68: Data Tlb Multiple Hit Exception
3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.
Page 69: Data Tlb Protection Violation Exception
Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry.
Page 70: Initial Page Write Exception
Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains...
Page 71: Memory-Mapped Tlb Configuration
Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3.
Page 72: Itlb Address Array
3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field.
Page 73: Itlb Data Array 1
3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.
Page 74: Itlb Data Array 2
3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 75 In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0].
Page 76: Utlb Data Array 1
3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field.
Page 77: Utlb Data Array 2
3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 78: Caches
4.1.1 Features The SH7750 Series has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) can also be used as on-chip RAM. The features of these caches are summarized in table 4.1.
Page 79: Register Configuration
4.1.2 Register Configuration Table 4.2 shows the cache control registers. Table 4.2 Cache Control Registers Initial Area 7 Access Name Abbreviation R/W Value* Address* Address* Size Cache control H'0000 0000 H'FF00 001C H'1F00 001C register Queue address QACR0 Undefined H'FF00 0038 H'1F00 0038 control register 0 Queue address...
Page 80 (1) Cache Control Register (CCR): CCR contains the following bits: IIX: IC index enable ICI: IC invalidation ICE: IC enable OIX: OC index enable ORA: OC RAM enable OCI: OC invalidation Copy-back enable Write-through enable OCE: OC enable Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in area 7.
Page 81 • OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode •...
Page 82: Operand Cache (Oc)
Operand Cache (OC) 4.3.1 Configuration Figure 4.2 shows the configuration of the operand cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 RAM area determination [11:5] [13] [12] Longword (LW) selection Address array Data array 19 bits 1 bit 1 bit 32 bits...
Page 83: Read Operation
The operand cache consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32- byte data. • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 84: Write Operation
3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address.
Page 85 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. 3b.
Page 86: Write-Back Buffer
4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, the SH7750 Series has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination.
Page 87: Oc Index Mode
• When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 kB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 kB): Corresponds to RAM area 1 RAM areas 1 and 2 then repeat every 8 kbytes up to H'7FFF FFFF.
Page 88: Coherency Between Cache And External Memory
Prefetch Operation The SH7750 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance.
Page 89: Instruction Cache (Ic)
Instruction Cache (IC) 4.4.1 Configuration Figure 4.5 shows the configuration of the instruction cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 [11:5] [12] Longword (LW) selection Address array Data array 19 bits 1 bit 32 bits 32 bits 32 bits...
Page 90: Read Operation
The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32- byte data (16 instructions). • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 91: Ic Index Mode
4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two 4-kbyte areas by means of effective address bit [25], providing efficient use of the cache.
Page 92: Ic Data Array
2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3.
Page 93: Oc Address Array
The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2.
Page 94 The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0.
Page 95: Oc Data Array
4.5.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field.
Page 96: Store Queues
Store Queues The SH7750 Series supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S, if the SQs are not used the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.
Page 97 memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external memory address bit [28:0] specification is as shown below, according to whether the MMU is on or off.
Page 98: Sq Protection
4.6.4 SQ Protection Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. If an exception occurs in an SQ write, the SQ contents may be corrupted. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted.
Page 99: Exceptions
SH7750 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1.
Page 100: Register Descriptions
Register Descriptions There are three registers related to exception handling. These are allocated to memory, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.
Page 101: Exception Handling Functions
Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 102: Exception Types And Priorities
Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Reset Abort type Power-on reset H'A000 0000 —...
Page 103 Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340...
Page 104: Exception Flow
Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral DMAC DMTE0 (VBR) H'600 H'640 type module DMTE1 H'660 interrupt DMTE2 H'680 (module/ source) DMTE3 H'6A0 DMAE H'6C0 SCIF H'700 H'720 H'740...
Page 105: Exception Source Acceptance
Reset requested? Execute next instruction Is highest- General priority exception exception requested? re-exception type? Cancel instruction execution result Interrupt requested? SSR ← SR EXPEVT ← exception code SPC ← PC SR. {MD, RB, BL, FD, IMASK} ← 11101111 SGR ← R15 PC ←...
Page 106 Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Instruction fetch ID: Instruction decode EX: Instruction execution Instruction n+3 MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling:...
Page 107: Exception Requests And Bl Bit
5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 108: Resets
5.6.1 Resets (1) Power-On Reset • Sources:  SCK2 pin high level and 5(6(7 pin low level  When the watchdog timer overflows while the WT/,7 bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. •...
Page 109 (2) Manual Reset • Sources:  SCK2 pin low level and 5(6(7 pin low level  When a general exception other than a user break occurs while the BL bit is set to 1 in SR  When the watchdog timer overflows while the WT/,7 bit and RSTS bit are both set to 1 in WTCSR.
Page 110 (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111.
Page 111 (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 112 (5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 113: General Exceptions
5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 114 (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 115 (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 116 (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible Read/write access possible...
Page 117 (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H'0000 0100 •...
Page 118 (6) Data Address Error • Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)  Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ...
Page 119 (7) Instruction Address Error • Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 120 (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 121 (9) General Illegal Instruction Exception • Sources:  Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 122 (10) Slot Illegal Instruction Exception • Sources:  Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR ...
Page 123 (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 124 (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 125 (13) User Breakpoint Trap • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'0000 0100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 126 (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 127: Interrupts
5.6.3 Interrupts (1) NMI • Source: NMI pin edge detection • Transition address: VBR + H'0000 0600 • Transition operations: The contents of PC and SR immediately after the instruction at which this interrupt was accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 128 (2) IRL Interrupts • Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'0000 0600 • Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC.
Page 129 (3) Peripheral Module Interrupts • Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). •...
Page 130: Priority Order With Multiple Exceptions
5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 131: Usage Notes
Usage Notes 1. Return from exception handling a. Check the BL bit in SR with software. If SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR contents are set in SR, and branch is made to the SPC address to return from the exception handling routine.
Page 132: Restrictions
Restrictions 1. Restrictions on first instruction of exception handling routine • Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. • When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register.
Page 133: Floating-Point Unit
A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) The SH7750 Series can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 23 22 Figure 6.1 Format of Single-Precision Floating-Point Number...
Page 134 52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1. The two values E –...
Page 135: Non-Numbers (Nan)
Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000 Positive normalized H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to number H'00100000 00000000 Positive denormalized...
Page 136: Denormalized Numbers
EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7750 Series as operation results are as follows: • Single-precision qNaN: H'7FBFFFFF •...
Page 137: Registers
Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;...
Page 138 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14 FPR15_BANK0 FR15 XF15 FPR0_BANK1...
Page 139: Floating-Point Status/Control Register (Fpscr)
6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 140: Floating-Point Communication Register (Fpul)
• Bits 22 to 31: Reserved These bits are always read as 0, and should only be written with 0. Notes: The following functions have been added to the FPU of the SH7750 Series (not provided in the FPU of the SH7718): 1.
Page 141: Floating-Point Exceptions
0, but the corresponding bit in the flag field remains unchanged. • Enable/disable exception handling The SH7750 Series supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases:  FPU error (E): FPSCR.DN = 0 and a denormalized number is input ...
Page 142: Graphics Support Functions
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.  Inexact exception (I): An inexact result is generated. Graphics Support Functions The SH7750 Series supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations.
Page 143 This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 × 4 matrix, the SH7750 Series supports 4-dimensional operations. • Matrix (4 × 4) × matrix (4 × 4): This operation requires the execution of four FTRV instructions.
Page 144: Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, the SH7750 Series also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the SH7750 Series can perform data transfer by means of pair single- precision data transfer instructions. • FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) •...
Page 145: Instruction Set
PC: At the start of instruction execution, PC indicates the address of the instruction itself. Data sizes and data types: The SH7750 Series’ instruction set is implemented with 16-bit fixed- length instructions. The SH7750 Series can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access.
Page 146 In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution.
Page 147: Addressing Modes
Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 148 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), Word: Rn +...
Page 149 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size.
Page 150 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp × 2 → Branch- disp added after being sign-extended and multiplied by 2.
Page 151: Instruction Set
Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand →, ← Summary of Transfer direction operation...
Page 152 Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — (disp × 2 + PC + 4) → sign MOV.W @(disp,PC),Rn 1001nnnndddddddd — — extension → Rn (disp × 4 + PC & H'FFFFFFFC MOV.L @(disp,PC),Rn 1101nnnndddddddd —...
Page 153 Table 7.3 Fixed-Point Transfer Instructions (cont) Instruction Operation Instruction Code Privileged T Bit R0 → (disp + GBR) MOV.B R0,@(disp,GBR) 11000000dddddddd — — R0 → (disp × 2 + GBR) MOV.W R0,@(disp,GBR) 11000001dddddddd — — R0 → (disp × 4 + GBR) MOV.L R0,@(disp,GBR) 11000010dddddddd —...
Page 154 Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100 — — Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii — — Rn + Rm + T → Rn, carry → T ADDC Rm,Rn 0011nnnnmmmm1110 —...
Page 155 Table 7.4 Arithmetic Operation Instructions (cont) Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word → Rn EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte → Rn EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 —...
Page 156 Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —...
Page 157 Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — LSB → Rn → T ROTR 0100nnnn00000101 — T ← Rn ← T ROTCL 0100nnnn00100100 — T → Rn → T ROTCR 0100nnnn00100101 —...
Page 158 Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — 4 → PC When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd —...
Page 159 Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit 0 → MACH, MACL CLRMAC 0000000000101000 — — 0 → S CLRS 0000000001001000 — — 0 → T CLRT 0000000000001000 — Rm → SR Rm,SR 0100mmmm00001110 Privileged Rm → GBR Rm,GBR 0100mmmm00011110 —...
Page 160 Table 7.8 System Control Instructions (cont) Instruction Operation Instruction Code Privileged T Bit 1 → S SETS 0000000001011000 — — 1 → T SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR → Rn SR,Rn 0000nnnn00000010 Privileged — GBR →...
Page 161 Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H'00000000 → FRn FLDI0 1111nnnn10001101 — — H'3F800000 → FRn FLDI1 1111nnnn10011101 — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — — (Rm) → FRn FMOV.S @Rm,FRn 1111nnnnmmmm1000 — —...
Page 162 Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — FFFF → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 — — When DRn = DRm, 1 → T FCMP/EQ DRm,DRn 1111nnn0mmm00100 —...
Page 163 Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn 1111nnn1mmm01100 — — XDm → DRn FMOV XDm,DRn 1111nnn0mmm11100 — — XDm → XDn FMOV XDm,XDn 1111nnn1mmm11100 — — (Rm) → XDn FMOV @Rm,XDn 1111nnn1mmmm1000 —...
Page 164: Pipelining
Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7750 Series. Pipelines Figure 8.1 shows the basic pipelines.
Page 165 1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction • Address •...
Page 166 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.
Page 167 10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.
Page 168 19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.
Page 169 31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.
Page 170 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle Notes: : Cannot overlap a stage of the same kind, except when two instructions are executed in parallel.
Page 171: Parallel-Executability
Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.
Page 172 Table 8.1 Instruction Groups (cont) 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W...
Page 173 Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV...
Page 174 Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L...
Page 175: Execution Cycles And Pipeline Stalling
Table 8.2 Parallel-Executability 2nd Instruction Instruction O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: •...
Page 176 The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 177 Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)).
Page 178 (a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction. (b) Parallel execution: parallel-executable and no dependency 1 issue cycle EX-group ADD and LS-group MOV.L can...
Page 179 (e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result MOV.L @R1,R1 of ADD as its destination address.
Page 180 (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,R1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency 11-cycle latency FSQRT FR4 FMOV FR0,FR4 10 stall cycles = latency (11) - 1 The registers are written-back in program order.
Page 181 (h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR GBR,R2 3 stall cycles FADD DR0,DR2 MAC.W @R1+,@R2+ 5 stall cycles...
Page 182 Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data EXTS.B Rm,Rn — — — transfer EXTS.W Rm,Rn — — — instructions EXTU.B Rm,Rn — — — EXTU.W Rm,Rn —...
Page 183 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data MOV.W R0,@(disp,Rn) — — — transfer MOV.L Rm,@(disp,Rn) — — — instructions MOV.B Rm,@(R0,Rn) — — — MOV.W Rm,@(R0,Rn) —...
Page 184 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn — — — MAC.L @Rm+,@Rn+ 2/2/4/4...
Page 185 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — — — SHAD Rm,Rn —...
Page 186 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS — — — SETT —...
Page 187 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn — — — SPC,Rn —...
Page 188 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Single- FABS — — — precision FADD FRm,FRn — — — floating-point FCMP/EQ FRm,FRn — — — instructions FCMP/GT FRm,FRn —...
Page 189 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage S