Figure 22.36 (B) Synchronous Dram Bus Cycle: Synchronous Dram Mode Register Setting (Set) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register

Setting (SET)

Rev. 6.0, 07/02, page 899 of 986

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