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Figure 22.40 Dram Burst Bus Cycle (Edo Mode, Rcd[1:0] = 01, Anw[2:0] = 001, Tpc[2:0] = 001) - Hitachi SH7750 Hardware Manual

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Figure 22.40 DRAM Burst Bus Cycle

(EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001)

Rev. 6.0, 07/02, page 903 of 986

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