Hitachi SH7750 Hardware Manual page 929

CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
T1 Tw Twe
t
AD
t
CSD
t
RWD
t t
RSD RSD
t
WED1
t
WEDF
t t
WDD WDD
t t
BSD BSD
t
RDYS
t
RDYS
t
DACD
t
DACD
t
DACDF
t
DACD
T2
t
AD
t
CSD
t
RWD
t
RSD
t t
RDS RDH
t
WEDF
t
WDD
t
RDYH
t
RDYH
t
DACD
t
DACDF
t
DACD
Rev. 6.0, 07/02, page 879 of 986