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E.1
Pin States
Table E.1
Pin States in Reset, Power-Down State, and Bus-Released State
Signal Name
I/O
D0–D7
I/O
D8–D15
I/O
D16–D23
I/O
D24–D31
I/O
D32–D51
I/O
D52–D55
I/O
D56–D63
I/O
A0, A1, A18–A25
O
A2–A17
O
RESET
I
BACK/BSREQ
O
BREQ/BSACK
I
BS
O
CKE
O
CS6–CS0
O
RAS
O
RD/CASS
O
RD/WR
O
RDY
I
WE7/CAS7/DQM7
O
WE6/CAS6/DQM6
O
WE5/CAS5/DQM5
O
WE4/CAS4/DQM4
O
WE3/CAS3/DQM3
O
Appendix E Pin Functions
Reset
(Power-On)
Master Slave
Master Slave
15
15
15
Z *
Z *
Z *
Z *
15
Z *
15
Z *
15
15
15
15
Z *
Z *
Z *
15
15
15
Z *
Z *
Z *
Z *
15
Z *
15
ZK *
Z *
15
Z *
15
Z *
15
15
15
15
Z *
Z *
Z *
16
16
14
Z *
Z *
Z *
16
16
14
Z *
Z *
Z *
I
I
I
H
H
H
I *
16
I *
16
I *
13
16
Z *
H
H
O *
H
H
Z *
16
H
H
16
Z *
O *
H
16
Z *
O *
H
Z *
16
H
H
16
16
13
PI *
PI *
I *
16
Z *
O *
H
Z *
16
O *
H
16
Z *
O *
H
16
Z *
O *
H
16
Z *
O *
H
Reset
(Manual)
Standby
15
15
Z *
Z *
Z *
15
Z *
15
15
15
Z *
Z *
15
15
Z *
Z *
15
ZK *
15
Z *
15
K
Z *
15
Z *
15
15
15
Z *
Z *
17
14
14
7
O *
Z *
Z *
O *
9
14
14
7
O *
Z *
Z *
O *
I
I
H
H
I *
13
I *
13
14
14
7
Z *
Z *
H *
6
6
O *
L
Z *
14
Z *
14
H *
7
6
14
14
5
Z *
Z *
O *
6
14
14
5
Z *
Z *
O *
Z *
14
Z *
14
H *
7
13
13
I *
I *
6
14
14
5
Z *
Z *
O *
6
Z *
14
Z *
14
O *
5
6
14
14
5
Z *
Z *
O *
6
14
14
5
Z *
Z *
O *
6
14
14
5
Z *
Z *
O *
Rev. 6.0, 07/02, page 951 of 986
Hard-
Bus
ware
Released
Standby Notes
15
Z *
Z
Z *
15
Z
15
Z *
Z
15
Z *
Z
Z *
15
K
Z
Output
state held
when used
as port
Z *
15
Z
15
Z *
Z
14
Z *
Z
14
Z *
Z
I
I
O
Z
I *
13
I
14
Z *
Z
6
O *
Z
Z *
14
Z
14
5
Z *
O *
Z
14
5
Z *
O *
Z
Z *
14
Z
13
I *
I
14
5
Z *
O *
Z
Z *
14
O *
5
Z
14
5
Z *
O *
Z
14
5
Z *
O *
Z
14
5
Z *
O *
Z
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