Standby Control Register 2 (Stbcr2) - Hitachi SH7750 Hardware Manual

9.2.4

Standby Control Register 2 (STBCR2)

Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep
mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via
the RESET pin or due to watchdog timer overflow.
Bit:
Initial value:
R/W:
Notes: *1 Reserved bit in the SH7750.
*2 Reserved bit in the SH7750 and SH7750S.
Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
0
1
Note: * When the STBY bit in the STBCR register is 0
Bit 6 (SH7750R Only)—STATUS Pin High-Impedance Control (STHZ): This bit selects
whether the STATUS0 and 1 pins are set to high-impedance when in hardware standby mode.
Bit 6: STHZ
0
1
Bit 6 (SH7750 and SH7750S)—Reserved: Only 0 should only be written to these bits; operation
cannot be guaranteed if 1 is written. These bits are always read as 0.
Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Bits 1 and 0 (SH7750)—Reserved: Only 0 should only be written to these bits; operation cannot
be guaranteed if 1 is written. These bits are always read as 0.
7 6
2
STHZ *
DSLP
0 0
R/W R/W
Description
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
Transition to deep sleep mode on execution of SLEEP instruction*
Description
Sets STATUS0, 1 pins to high-impedance when in hardware standby mode
Drives STATUS0, 1 pins to LH when in hardware standby mode
5 4 3
— — —
0 0 0
R R R
2 1
MSTP6 *
—
0 0
R R/W
(Initial value)
Rev. 6.0, 07/02, page 227 of 986
0
1 1
MSTP5 *
0
R/W